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DS25BR101

更新时间： 2024-11-06 06:54:39

品牌	Logo	应用领域
美国国家半导体 - NSC		/
页数	文件大小	规格书
16页	472K
描述
3.125 Gbps LVDS Buffer with Transmit Pre-Emphasis and Receive Equalization

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中文翻译

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DS25BR101 数据手册

August 11, 2009

DS25BR100 / DS25BR101

3.125 Gbps LVDS Buffer with Transmit Pre-Emphasis and

Receive Equalization

General Description

Features

The DS25BR100 and DS25BR101 are single channel 3.125

Gbps LVDS buffers optimized for high-speed signal trans-

mission over lossy FR-4 printed circuit board backplanes and

balanced metallic cables. Fully differential signal paths en-

sure exceptional signal integrity and noise immunity.

DC - 3.125 Gbps low jitter, high noise immunity, low power

■

operation

Receive equalization reduces ISI jitter due to media loss

■

Transmit pre-emphasis drives lossy backplanes and

cables

The DS25BR100 and DS25BR101 feature transmit pre-em-

phasis (PE) and receive equalization (EQ), making them ideal

for use as a repeater device. Other LVDS devices with similar

IO characteristics include the following products. The

DS25BR120 features four levels of pre-emphasis for use as

an optimized driver device, while the DS25BR110 features

four levels of equalization for use as an optimized receiver

device. The DS25BR150 is a buffer/repeater with the lowest

power consumption and does not feature transmit pre-em-

phasis nor receive equalization.

On-chip 100Ω input and output termination minimizes

insertion and return losses, reduces component count and

minimizes board space. The DS25BR101 eliminates the

on-chip input termination for added design flexibility.

7 kV ESD on LVDS I/O pins protects adjoining

components

■

Small 3 mm x 3 mm LLP-8 space saving package

Applications

Wide input common mode range allows the receiver to accept

signals with LVDS, CML and LVPECL levels; the output levels

are LVDS. A very small package footprint requires minimal

space on the board while the flow-through pinout allows easy

board layout. On the DS25BR100 the differential input and

output is internally terminated with a 100Ω resistor to lower

return losses, reduce component count and further minimize

board space. For added design flexibility the 100Ω input ter-

minations on the DS25BR101 have been eliminated. This

enables a designer to adjust the termination for custom inter-

connect topologies and layout.

Clock and data buffering

■

Metallic cable driving and equalization

FR-4 equalization

Typical Application

20179110

201791

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中文翻译

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与DS25BR101相关器件

型号	品牌	获取价格	描述	数据表
DS25BR101TSD	NSC	获取价格	3.125 Gbps LVDS Buffer with Transmit Pre-Emphasis and Receive Equalization
DS25BR101TSD/NOPB	TI	获取价格	具有发送预加重和接收均衡功能的 3.125Gbps LVDS 缓冲器 \| NGQ \| 8
DS25BR101TSDE/NOPB	TI	获取价格	具有发送预加重和接收均衡功能的 3.125Gbps LVDS 缓冲器 \| NGQ \| 8
DS25BR101TSDX	NSC	获取价格	3.125 Gbps LVDS Buffer with Transmit Pre-Emphasis and Receive Equalization
DS25BR101TSDX/NOPB	TI	获取价格	具有发送预加重和接收均衡功能的 3.125Gbps LVDS 缓冲器 \| NGQ \| 8
DS25BR110	NSC	获取价格	3.125 Gbps LVDS Buffer with Receive Equalization
DS25BR110	TI	获取价格	具有接收均衡功能的 3.125Gbps LVDS 缓冲器
DS25BR110_0711	NSC	获取价格	3.125 Gbps LVDS Buffer with Receive Equalization
DS25BR110TSD	NSC	获取价格	3.125 Gbps LVDS Buffer with Transmit Pre-Emphasis and Receive Equalization
DS25BR110TSD/NOPB	NSC	获取价格	IC LINE DRIVER, DSO8, 3 X 3 MM, GREEN, LLP-8, Line Driver or Receiver

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