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DAC5675AIPHPR PDF预览

DAC5675AIPHPR

更新时间： 2024-11-29 12:43:55
品牌 Logo 应用领域
德州仪器 - TI 转换器数模转换器
页数 文件大小 规格书
26页 1002K
描述
14-Bit, 400MSPS Digital-to-Analog Converter

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DAC5675AIPHPR 技术参数

是否Rohs认证： 符合生命周期：Obsolete
零件包装代码：QFP包装说明：GREEN, PLASTIC, HTQFP-48
针数：48Reach Compliance Code：compliant
Factory Lead Time：1 week风险等级：5.79
Is Samacsys：N最大模拟输出电压：3.9 V
最小模拟输出电压：2.15 V转换器类型：D/A CONVERTER
输入位码：BINARY输入格式：PARALLEL, WORD
JESD-30 代码：S-PQFP-G48JESD-609代码：e4
长度：7 mm最大线性误差 (EL)：0.0244%
湿度敏感等级：3位数：14
功能数量：1端子数量：48
最高工作温度：85 °C最低工作温度：-40 °C
封装主体材料：PLASTIC/EPOXY封装代码：HTFQFP
封装等效代码：TQFP48,.35SQ封装形状：SQUARE
封装形式：FLATPACK, HEAT SINK/SLUG, THIN PROFILE, FINE PITCH峰值回流温度（摄氏度）：260
电源：3.3 V认证状态：Not Qualified
座面最大高度：1.2 mm标称安定时间 (tstl)：0.012 µs
子类别：Other Converters标称供电电压：3.3 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式：GULL WING端子节距：0.5 mm
端子位置：QUAD处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：7 mmBase Number Matches：1

DAC5675AIPHPR 数据手册

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DAC5675A  
www.ti.com  
SBAS334C–NOVEMBER 2004–REVISED MARCH 2005  
14-Bit, 400MSPS Digital-to-Analog Converter  
FEATURES  
•
Power Dissipation: 660mW at fCLK = 400MSPS,  
fOUT = 20MHz  
•
•
•
400MSPS Update Rate  
•
Package: 48-Pin HTQFP PowerPad™,  
TJA = 28.8°C/W  
LVDS-Compatible Input Interface  
Spurious-Free Dynamic Range (SFDR) to  
Nyquist:  
APPLICATIONS  
•
– 69dBc at 70MHz IF, 400MSPS  
Cellular Base Transceiver Station Transmit  
Channel:  
– CDMA: WCDMA, CDMA2000, IS-95  
– TDMA: GSM, IS-136, EDGE/GPRS  
– Supports Single-Carrier and Multicarrier  
Applications  
Test and Measurement: Arbitrary Waveform  
Generation  
Direct Digital Synthesis (DDS)  
Cable Modem Headend  
•
W-CDMA Adjacent Channel Power Ratio  
(ACPR):  
– 73dBc at 30.72MHz IF, 122.88MSPS  
– 71dBc at 61.44MHz IF, 245.76MSPS  
•
Differential Scalable Current Sink Outputs:  
2mA to 20mA  
•
•
•
On-Chip 1.2V Reference  
•
•
Single 3.3V Supply Operation  
DESCRIPTION  
The DAC5675A is a 14-bit resolution high-speed digital-to-analog converter. The DAC5675A is designed for  
high-speed digital data transmission in wired and wireless communication systems, high-frequency direct-digital  
synthesis (DDS), and waveform reconstruction in test and measurement applications. The DAC5675A has  
excellent spurious-free dynamic range (SFDR) at high intermediate frequencies, which makes the DAC5675A  
well-suited for multicarrier transmission in TDMA- and CDMA-based cellular base transceiver stations (BTSs).  
The DAC5675A operates from a single-supply voltage of 3.3V. Power dissipation is 660mW at fCLK = 400MSPS,  
fOUT = 70MHz. The DAC5675A provides a nominal full-scale differential current output of 20mA, supporting both  
single-ended and differential applications. The output current can be directly fed to the load with no additional  
external output buffer required. The output is referred to the analog supply voltage AVDD  
.
The DAC5675A comprises a low-voltage differential signaling (LVDS) interface for high-speed digital data input.  
LVDS features a low differential voltage swing with a low constant power consumption across frequency,  
allowing for high-speed data transmission with low noise levels; that is, with low electromagnetic interference  
(EMI). LVDS is typically implemented in low-voltage digital CMOS processes, making it the ideal technology for  
high-speed interfacing between the DAC5675A and high-speed low-voltage CMOS ASICs or FPGAs. The  
DAC5675A current-sink-array architecture supports update rates of up to 400MSPS. On-chip edge-triggered  
input latches provide for minimum setup and hold times, thereby relaxing interface timing.  
The DAC5675A has been specifically designed for a differential transformer-coupled output with a 50Ω doubly-  
terminated load. With the 20mA full-scale output current, both a 4:1 impedance ratio (resulting in an output power  
of 4dBm) and 1:1 impedance ratio transformer (–2dBm) are supported. The last configuration is preferred for  
optimum performance at high output frequencies and update rates. The outputs are terminated to AVDD and  
have voltage compliance ranges from AVDD – 1 to AVDD + 0.3V.  
An accurate on-chip 1.2V temperature-compensated bandgap reference and control amplifier allows the user to  
adjust this output current from 20mA down to 2mA. This provides 20dB gain range control capabilities.  
Alternatively, an external reference voltage may be applied. The DAC5675A features a SLEEP mode, which  
reduces the standby power to approximately 18mW.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
PowerPad is a trademark of Texas Instruments.  
All trademarks are the property of their respective owners.  
PRODUCTION DATA information is current as of publication date.  
Copyright © 2004–2005, Texas Instruments Incorporated  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
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DAC5675AIPHPR 替代型号

型号 品牌 替代类型 描述 数据表
DAC5675AIPHP TI

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