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DAC5682ZIRGC

更新时间： 2024-11-21 13:07:19
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德州仪器 - TI 数字信号处理器
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DAC5682ZIRGC 数据手册

 浏览型号DAC5682ZIRGC的Datasheet PDF文件第2页浏览型号DAC5682ZIRGC的Datasheet PDF文件第3页浏览型号DAC5682ZIRGC的Datasheet PDF文件第4页浏览型号DAC5682ZIRGC的Datasheet PDF文件第5页浏览型号DAC5682ZIRGC的Datasheet PDF文件第6页浏览型号DAC5682ZIRGC的Datasheet PDF文件第7页 
GC5330  
GC5337  
www.ti.com  
SLWS226 B –DECEMBER 2010–REVISED JANUARY 2011  
Wideband Transmit-Receive Digital Signal Processors  
Check for Samples: GC5330, GC5337  
1
FEATURES  
APPLICATIONS  
•
•
•
•
•
•
•
Multi-Standard Base Stations  
3GPP (LTE, W-CDMA, TDS-CDMA)  
MC-GSM  
WiMAX and WiBro (OFDMA)  
Multi-Carrier Power Amplifiers (MCPAs)  
Wireless Infrastructure Repeaters  
Up to 4 × 4 MIMO  
•
Integrated Transmit and Receive Digital IF  
Solution  
•
•
Up to 4 TX, 8 RX, Plus DPD Feedback  
TX-Transmit Includes DUC, CFR, DPD, TX  
Equalizer, and Bulk Upconverter  
•
•
62-MHz TX Signal Bandwidth With Fifth-Order  
DPD Correction  
CFR: 6-dB PAR for WCDMA, 7-db LTE Signals  
With EVM Meeting 3GPP Specs; Configurable  
for All Major Wireless Infrastructure Standards  
DESCRIPTION  
The GC533x is a wideband transmit and receive  
signal processor that includes digital downconverter /  
upconverter (DDUC), transmit, receive, and capture  
buffer blocks. The transmit path includes crest factor  
reduction (CFR), digital predistortion (DPD) and  
associated feedback path, complex equalization, and  
bulk upconversion.  
•
•
DPD: Memory Compensation, Typical ACLR  
Improvement of 20 dB or More  
RX-Receive Includes DC-Offset Cancellation,  
Front-End and Back-End AGC, Bulk  
Downconverter, RX Equalizer, I/Q Imbalance  
Correction, DDC  
The receive path includes wideband and narrowband  
automatic gain control (AGC), bulk downconversion,  
complex equalization, and I/Q imbalance correction.  
•
4 DDUCs, 1–12 Channels per DDUC, Each  
DDUC Can Be Programmed to TX or RX, at a  
Common Resampler Rate – Multimode  
Support  
The DDUC section consists of four identical DDUC  
blocks, each supporting up to 12 channels. Each  
channel has independent fractional resamplers and  
NCOs to enable flexible carrier configurations.  
Multi-mode/multi-standard  
supported by configuring the individual DDUC blocks  
to different filtering and oversampling scenarios.  
•
•
•
Seamless Interface to TI High-Speed Data  
Converters  
4 TX Aggregate Output to DACs up to  
930 MSPS Complex  
operation  
can  
be  
8 RX Aggregate Input From ADCs up to  
1.24 GSPS Real  
DAC3484  
TRF3703/3720  
I/Q Mod  
C6748  
DSP  
Complex  
TX  
PA  
PA  
PA  
PA  
•
•
•
Supports Envelope Tracking Techniques  
16-Tap (Complex) RX Equalizers  
DAC  
I/Q  
I/Q Mod  
I/Q Mod  
I/Q Mod  
Two 4K Complex Word Capture Buffers for  
Signal Analysis, Adaptive Filtering, and DPD  
Algorithms  
DAC  
I/Q  
FB  
•
•
•
•
TMS320C6748 DPD Optimization Software  
1.1-V Core, 3.3-V I/O CMOS, 1.8-V I/O LVDS  
Power Consumption, 3.5 W Typical  
ADS61B49  
ADC  
Subsampled  
Feedback  
SW  
Mixer/BPF  
Baseband  
Data  
GC533x  
DUC-CFR  
DPD  
ADS62P49  
ADC  
DDC  
RX  
RX  
Mixer/BPF  
Mixer/BPF  
LNA  
484-Ball TE-PBGA Package, 23 mm × 23 mm  
Real  
RX  
ADC  
LNA  
ADS62P49  
ADC  
RX  
RX  
Mixer/BPF  
Mixer/BPF  
LNA  
LNA  
Real  
RX  
ADC  
B0441-01  
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
© 2010–2011, Texas Instruments Incorporated  
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