DAC5675A-SP
www.ti.com ..................................................................................................................................................... SGLS387D –JULY 2007–REVISED OCTOBER 2009
CLASS V, 14-BIT, 400-MSPS DIGITAL-TO-ANALOG CONVERTER
Check for Samples: DAC5675A-SP
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FEATURES
•
•
QML-V Qualified, SMD 5962-07204
•
•
•
400-MSPS Update Rate
Military Temperature Range (–55°C to 125°C)
LVDS-Compatible Input Interface
APPLICATIONS
•
Spurious-Free Dynamic Range (SFDR) to
Nyquist
Cellular Base Transceiver Station Transmit
Channel:
–
69 dBc at 70 MHz IF, 400 MSPS
–
–
–
CDMA: WCDMA, CDMA2000, IS-95
TDMA: GSM, IS-136, EDGE/GPRS
Supports Single-Carrier and Multicarrier
Applications
•
W-CDMA Adjacent Channel Power Ratio
(ACPR)
–
–
73 dBc at 30.72 MHz IF, 122.88 MSPS
71 dBc at 61.44 MHz IF, 245.76 MSPS
•
Test and Measurement: Arbitrary Waveform
Generation
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Differential Scalable Current Outputs:
2 mA to 20 mA
•
•
•
On-Chip 1.2-V Reference
Single 3.3-V Supply Operation
Power Dissipation: 660 mW at
fCLK = 400 MSPS, fOUT = 20 MHz
•
High-Performance 52-Pin Ceramic Quad Flat
Pack (HFG)
DESCRIPTION/ORDERING INFORMATION
The DAC5675A is a 14-bit resolution high-speed digital-to-analog converter (DAC). The DAC5675A is designed
for high-speed digital data transmission in wired and wireless communication systems, high-frequency direct
digital synthesis (DDS), and waveform reconstruction in test and measurement applications. The DAC5675A has
excellent spurious-free dynamic range (SFDR) at high intermediate frequencies, which makes it well suited for
multicarrier transmission in TDMA and CDMA based cellular base transceiver stations (BTSs).
The DAC5675A operates from a single supply voltage of 3.3 V. Power dissipation is 660 mW at
fCLK = 400 MSPS, fOUT = 70 MHz. The DAC5675A provides a nominal full-scale differential current output of
20 mA, supporting both single-ended and differential applications. The output current can be directly fed to the
load with no additional external output buffer required. The output is referred to the analog supply voltage AVDD
.
The DAC5675A includes a low-voltage differential signaling (LVDS) interface for high-speed digital data input.
LVDS features a low differential voltage swing with a low constant power consumption across frequency,
allowing for high-speed data transmission with low noise levels; that is, with low electromagnetic interference
(EMI). LVDS is typically implemented in low-voltage digital CMOS processes, making it the ideal technology for
high-speed interfacing between the DAC5675A and high-speed low-voltage CMOS ASICs or FPGAs. The
DAC5675A current-source-array architecture supports update rates of up to 400 MSPS. On-chip edge-triggered
input latches provide for minimum setup and hold times, thereby relaxing interface timing.
The DAC5675A is specifically designed for
a differential transformer-coupled output with a 50-Ω
doubly-terminated load. With the 20-mA full-scale output current, both a 4:1 impedance ratio (resulting in an
output power of 4 dBm) and 1:1 impedance ratio transformer (–2 dBm) is supported. The last configuration is
preferred for optimum performance at high output frequencies and update rates. The outputs are terminated to
AVDD and have voltage compliance ranges from AVDD – 1 to AVDD + 0.3 V.
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Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright © 2007–2009, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
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