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CYW312OXC PDF预览

CYW312OXC

更新时间: 2024-01-04 22:45:21
品牌 Logo 应用领域
SPECTRALINEAR /
页数 文件大小 规格书
19页 193K
描述
FTG for VIA⑩ K7 Series Chipset with Programmable Output Frequency

CYW312OXC 技术参数

是否Rohs认证: 符合生命周期:Transferred
零件包装代码:SSOP包装说明:SSOP, SSOP48,.4
针数:48Reach Compliance Code:compliant
ECCN代码:EAR99HTS代码:8542.39.00.01
风险等级:5.51Is Samacsys:N
其他特性:ALSO REQUIRES 2.5V SUPPLYJESD-30 代码:R-PDSO-G48
JESD-609代码:e4长度:15.875 mm
湿度敏感等级:3端子数量:48
最高工作温度:70 °C最低工作温度:
最大输出时钟频率:200 MHz封装主体材料:PLASTIC/EPOXY
封装代码:SSOP封装等效代码:SSOP48,.4
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, SHRINK PITCH
峰值回流温度(摄氏度):260电源:2.5/3.3 V
主时钟/晶体标称频率:14.31818 MHz认证状态:Not Qualified
座面最大高度:2.794 mm子类别:Clock Generators
最大供电电压:3.465 V最小供电电压:3.135 V
标称供电电压:3.3 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)端子形式:GULL WING
端子节距:0.635 mm端子位置:DUAL
处于峰值回流温度下的最长时间:20宽度:7.5057 mm
uPs/uCs/外围集成电路类型:CLOCK GENERATOR, PROCESSOR SPECIFICBase Number Matches:1

CYW312OXC 数据手册

 浏览型号CYW312OXC的Datasheet PDF文件第13页浏览型号CYW312OXC的Datasheet PDF文件第14页浏览型号CYW312OXC的Datasheet PDF文件第15页浏览型号CYW312OXC的Datasheet PDF文件第17页浏览型号CYW312OXC的Datasheet PDF文件第18页浏览型号CYW312OXC的Datasheet PDF文件第19页 
W312-02  
DC Electrical Characteristics: TA = 0°C to +70°C, VDD = 3.3V 5% and 2.5V 5% (continued)  
Parameter  
Description  
Test Condition  
Min.  
Typ.  
Max.  
Unit  
Crystal Oscillator  
VTH  
X1 Input Threshold Voltage[4]  
VDD = 3.3V  
1.65  
18  
V
CLOAD  
Load Capacitance, Imposed on  
External Crystal[5]  
pF  
CIN,X1  
X1 Input Capacitance[6]  
Pin X2 unconnected  
Except X1 and X2  
TBD  
pF  
Pin Capacitance/Inductance  
CIN Input Pin Capacitance  
COUT  
LIN  
5
6
7
pF  
pF  
nH  
Output Pin Capacitance  
Input Pin Inductance  
AC Electrical Characteristics  
TA = 0°C to +70°C, VDDQ3 = 3.3V 5ꢀ, fXTL = 14.31818 MHz  
AC clock parameters are tested and guaranteed over stated operating conditions using the stated lump capacitive load at the  
clock output; Spread Spectrum is disabled.  
CPU Clock Outputs (CPUT0, CPUC0, CPU_CS)[7]  
CPU = 100 MHz  
CPU = 133 MHz  
Parameter  
tR  
Description  
Test Condition/Comments  
Min. Typ. Max. Min. Typ. Max. Unit  
Output Rise Edge Rate CPU_CS  
Output Fall Edge Rate CPU_CS  
1.0  
1.0  
45  
4.0  
4.0  
55  
1.0  
1.0  
45  
4.0 V/ns  
4.0 V/ns  
tF  
tD  
Duty Cycle  
Measured at 50% point  
55  
%
ps  
tJC  
fST  
Jitter, Cycle to Cycle  
250  
250  
Frequency Stabilization Assumes full supply voltage reached  
3
3
ms  
from Power-up (cold  
start)  
within 1 ms from power-up. Short  
cycles exist prior to frequency  
stabilization.  
Zo  
AC Output Impedance VO = VX  
50  
50  
:
Notes:  
5. The W312-02 contains an internal crystal load capacitor between pin X1 and ground and another between pin X2 and ground. Total load placed on crystal is  
18 pF; this includes typical stray capacitance of short PCB traces to crystal.  
6. X1 input capacitance is applicable when driving X1 with an external clock source (X2 is left unconnected).  
7. Refer to Figure 1 for K7 operation clock driver test circuit.  
Rev 1.0,November 27, 2006  
Page 16 of 19  

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