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CYW320OXC-3T PDF预览

CYW320OXC-3T

更新时间: 2024-11-28 02:52:27
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 晶体驱动器时钟发生器微控制器和处理器外围集成电路光电二极管
页数 文件大小 规格书
18页 303K
描述
200-MHz Spread Spectrum Clock Synthesizer/Driver

CYW320OXC-3T 技术参数

是否Rohs认证: 符合生命周期:Transferred
零件包装代码:SSOP包装说明:SSOP, SSOP56,.4
针数:56Reach Compliance Code:compliant
ECCN代码:EAR99HTS代码:8542.39.00.01
风险等级:5.5Is Samacsys:N
JESD-30 代码:R-PDSO-G56JESD-609代码:e4
长度:18.415 mm湿度敏感等级:3
端子数量:56最高工作温度:70 °C
最低工作温度:最大输出时钟频率:200 MHz
封装主体材料:PLASTIC/EPOXY封装代码:SSOP
封装等效代码:SSOP56,.4封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, SHRINK PITCH峰值回流温度(摄氏度):260
电源:3.3 V主时钟/晶体标称频率:14.31818 MHz
认证状态:Not Qualified座面最大高度:2.794 mm
子类别:Clock Generators最大压摆率:360 mA
最大供电电压:3.465 V最小供电电压:3.135 V
标称供电电压:3.3 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)端子形式:GULL WING
端子节距:0.635 mm端子位置:DUAL
处于峰值回流温度下的最长时间:20宽度:7.5 mm
uPs/uCs/外围集成电路类型:CLOCK GENERATOR, PROCESSOR SPECIFICBase Number Matches:1

CYW320OXC-3T 数据手册

 浏览型号CYW320OXC-3T的Datasheet PDF文件第2页浏览型号CYW320OXC-3T的Datasheet PDF文件第3页浏览型号CYW320OXC-3T的Datasheet PDF文件第4页浏览型号CYW320OXC-3T的Datasheet PDF文件第5页浏览型号CYW320OXC-3T的Datasheet PDF文件第6页浏览型号CYW320OXC-3T的Datasheet PDF文件第7页 
W320-03  
200-MHz Spread Spectrum Clock  
Synthesizer/Driver  
Benefits  
Features  
• Compliant with Intel® CK-Titan Clock Synthe-  
• Supports next-generation Pentium® processors using  
sizer/Driver Specifications  
differential clock drivers  
• Multiple output clocks at different frequencies  
• Three pairs of differential CPU outputs, up to 200 MHz  
• Ten synchronous PCI clocks, three free-running  
• Six 3V66 clocks  
• Two 48-MHz clocks  
• One reference clock at 14.318 MHz  
• One VCH clock  
• Motherboard clock generator  
• Support Multiple CPUs and a chipset  
• Support for PCI slots and chipset  
• Supports AGP, DRCG reference and Hub Link  
• Supports USB host controller and graphic controller  
• Supports ISA slots and I/O chip  
• Enables reduction of electromagnetic interference  
(EMI) and overall system cost  
• Spread Spectrum clocking (down spread)  
• Enables ACPI-compliant designs  
• Power-down features (PCI_STOP#, CPU_STOP#  
PWR_DWN#)  
• Supports up to four CPU clock frequencies  
• Enables ATE and “bed of nails” testing  
• Widely available, standard package enables lower cost  
• Three Select inputs (Mode select & IC Frequency  
Select)  
OE and Test Mode support  
56-pin SSOP package and 56-pin TSSOP package  
Logic Block Diagram  
Pin Configurations  
SSOP & TSSOP  
Top View  
VDD_REF  
REF  
REF  
VDD_REF  
XTAL_IN  
XTAL_OUT  
GND_REF  
PCI_F0  
1
2
3
4
5
6
56  
55  
54  
53  
52  
51  
50  
X1  
X2  
XTAL  
OSC  
PWR  
S1  
PLL Ref Freq  
S0  
CPU_STOP#  
Divider  
CPU0  
PLL 1  
Network  
PCI_F1  
PCI_F2  
CPU#0  
VDD_CPU  
CPU1  
VDD_CPU  
CPU0:2  
Stop  
Clock  
PWR  
7
Gate  
S0:2  
PWR_GD#  
Control  
VDD_PCI  
GND_PCI  
PCI0  
49  
48  
47  
46  
8
9
10  
11  
12  
13  
CPU#0:2  
CPU#1  
GND_CPU  
VDD_CPU  
CPU_STOP#  
VDD_PCI  
PCI_F0:2  
PCI1  
PCI2  
PWR  
CPU2  
CPU#2  
MULT0  
45  
44  
43  
42  
41  
Stop  
Clock  
PCI3  
PCI0:6  
Control  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
VDD_PCI  
GND_PCI  
PCI4  
PCI_STOP#  
PWR_DWN#  
IREF  
/2  
VDD_3V66  
3V66_0  
GND_IREF  
S2  
USB  
DOT  
VDD_ 48 MHz  
PWR  
PWR  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
PCI5  
PCI6  
VDD_3V66  
3V66_2:4/  
66BUFF0:2  
PWR  
3V66_5/ 66IN  
GND_3V66  
66BUFF0/3V66_2  
66BUFF1/3V66_3  
GND_ 48 MHz  
3V66_1/VCH  
PCI_STOP#  
3V66_0  
VDD_3V66  
GND_3V66  
VDD_48MHz  
USB (48MHz)  
PLL 2  
66BUFF2/3V66_4  
66IN/3V66_5  
DOT (48MHz)  
PWR_DWN#  
VDD_CORE  
GND_CORE  
VCH_CLK/ 3V66_1  
SCLK  
SDATA  
PWR_GD#  
SDATA  
SCLK  
SMBus  
Logic  
Cypress Semiconductor Corporation  
3901 North First Street  
San Jose, CA 95134  
408-943-2600  
Document #: 38-07248 Rev. *C  
Revised June 28, 2005  

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