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CYW320OXC-4

更新时间： 2024-11-28 02:52:27
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 驱动器时钟
页数 文件大小 规格书
17页 262K
描述
200-MHz Spread Spectrum Clock Synthesizer/Driver with Differential CPU Outputs

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中文翻译

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CYW320OXC-4 数据手册

 浏览型号CYW320OXC-4的Datasheet PDF文件第2页浏览型号CYW320OXC-4的Datasheet PDF文件第3页浏览型号CYW320OXC-4的Datasheet PDF文件第4页浏览型号CYW320OXC-4的Datasheet PDF文件第5页浏览型号CYW320OXC-4的Datasheet PDF文件第6页浏览型号CYW320OXC-4的Datasheet PDF文件第7页 
W320-04  
200-MHz Spread Spectrum Clock Synthesizer/Driver  
with Differential CPU Outputs  
Features  
Benefits  
• CompliantwithIntel® CK-Titanclocksynthesizer/driver  
• Supports next-generation Pentium® processors using  
specifications  
differential clock drivers  
• Multiple output clocks at different frequencies  
• Motherboard clock generator  
— Three pairs of differential CPU outputs, up to  
— Supports multiple CPUs and a chipset  
— Support for PCI slots and chipset  
— Supports AGP, DRCG reference, and Hub Link  
— Supports USB host controller and graphic controller  
— Supports ISA slots and I/O chip  
200 MHz  
— Ten synchronous PCI clocks, three free-running  
— Six 3V66 clocks  
— Two 48-MHz clocks  
— One reference clock at 14.318 MHz  
— One VCH clock  
• Enables reduction of electromagnetic interference  
(EMI) and overall system cost  
• Spread Spectrum clocking (down spread)  
• Enables ACPI-compliant designs  
• Power-down features (PCI_STOP#, CPU_STOP#  
• Supports up to four CPU clock frequencies  
• Enables ATE and “bed of nails” testing  
• Widely available standard package enables lower cost  
PWR_DWN#)  
• Three Select inputs (Mode select and IC Frequency  
Select)  
• OE and Test Mode support  
• 56-pin SSOP package and 56-pin TSSOP package  
Logic Block Diagram  
Pin Configurations  
SSOP and TSSOP  
Top View  
VDD_REF  
REF  
REF  
VDD_REF  
XTAL_IN  
XTAL_OUT  
GND_REF  
PCI_F0  
1
2
3
4
5
6
56  
55  
54  
53  
52  
51  
50  
X1  
X2  
XTAL  
OSC  
PWR  
S1  
S0  
PLL Ref Freq  
CPU_STOP#  
Divider  
CPU0  
PLL 1  
Network  
PCI_F1  
CPU#0  
VDD_CPU  
CPU1  
VDD_CPU  
CPU0:2  
Stop  
Clock  
PCI_F2  
7
PWR  
Gate  
S0:2  
PWR_GD#  
Control  
VDD_PCI  
GND_PCI  
PCI0  
49  
48  
47  
46  
8
9
10  
11  
12  
13  
CPU#0:2  
CPU#1  
GND_CPU  
VDD_CPU  
CPU_STOP#  
PCI1  
PCI2  
VDD_PCI  
PCI_F0:2  
PWR  
CPU2  
CPU#2  
MULT0#  
45  
44  
43  
42  
41  
Stop  
Clock  
PCI3  
PCI0:6  
Control  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
VDD_PCI  
GND_PCI  
PCI4  
IREF  
PCI_STOP#  
PWR_DWN#  
/2  
VDD_3V66  
3V66_0  
GND_IREF  
S2  
USB  
DOT  
VDD_ 48 MHz  
PWR  
PWR  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
PCI5  
PCI6  
VDD_3V66  
3V66_2:4/  
66BUFF0:2  
PWR  
3V66_5/ 66IN  
GND_3V66  
66BUFF0/3V66_2  
66BUFF1/3V66_3  
GND_ 48 MHz  
3V66_1/VCH  
PCI_STOP#  
3V66_0  
VDD_3V66  
GND_3V66  
VDD_48MHz  
USB (48MHz)  
PLL 2  
66BUFF2/3V66_4  
66IN/3V66_5  
DOT (48MHz)  
PWR_DWN#  
VDD_CORE  
GND_CORE  
VCH_CLK/ 3V66_1  
SCLK  
SDATA  
PWR_GD#  
SDATA  
SCLK  
SMBus  
Logic  
Cypress Semiconductor Corporation  
•
3901 North First Street  
•
San Jose, CA 95134  
•
408-943-2600  
Document #: 38-07010 Rev. *C  
Revised June 30, 2005  
1234567...17

中文翻译

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