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CYW320ZXC-4T PDF预览

CYW320ZXC-4T

更新时间: 2024-11-28 20:23:31
品牌 Logo 应用领域
芯科 - SILICON 时钟光电二极管外围集成电路晶体
页数 文件大小 规格书
16页 164K
描述
Processor Specific Clock Generator, 200MHz, CMOS, PDSO56, 6 X 12 MM, LEAD FREE, MO-153, TSSOP2-56

CYW320ZXC-4T 技术参数

生命周期:Active零件包装代码:TSSOP
包装说明:TSSOP,针数:56
Reach Compliance Code:unknownECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.5
Is Samacsys:NJESD-30 代码:R-PDSO-G56
长度:14 mm端子数量:56
最高工作温度:70 °C最低工作温度:
最大输出时钟频率:200 MHz封装主体材料:PLASTIC/EPOXY
封装代码:TSSOP封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH主时钟/晶体标称频率:14.318 MHz
座面最大高度:1.1 mm最大供电电压:3.465 V
最小供电电压:3.135 V标称供电电压:3.3 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子形式:GULL WING
端子节距:0.5 mm端子位置:DUAL
宽度:6.1 mmuPs/uCs/外围集成电路类型:CLOCK GENERATOR, PROCESSOR SPECIFIC
Base Number Matches:1

CYW320ZXC-4T 数据手册

 浏览型号CYW320ZXC-4T的Datasheet PDF文件第2页浏览型号CYW320ZXC-4T的Datasheet PDF文件第3页浏览型号CYW320ZXC-4T的Datasheet PDF文件第4页浏览型号CYW320ZXC-4T的Datasheet PDF文件第5页浏览型号CYW320ZXC-4T的Datasheet PDF文件第6页浏览型号CYW320ZXC-4T的Datasheet PDF文件第7页 
W320-04  
200 MHz Spread Spectrum Clock Synthesizer/Driver  
with Differential CPU Outputs  
Features  
Benefits  
• CompliantwithIntel® CK-Titanclocksynthesizer/driver  
specifications  
• Supports next-generation Pentium® processors using  
differential clock drivers  
• Multiple output clocks at different frequencies  
• Motherboard clock generator  
— Three pairs of differential CPU outputs, up to  
200 MHz  
— Supports multiple CPUs and a chipset  
— Support for PCI slots and chipset  
— Ten synchronous PCI clocks, three free-running  
— Six 3V66 clocks  
— Supports AGP, DRCG reference, and Hub Link  
— Supports USB host controller and graphic controller  
— Supports ISA slots and I/O chip  
— Two 48 MHz clocks  
— One reference clock at 14.318 MHz  
— One VCH clock  
• Enables reduction of electromagnetic interference  
(EMI) and overall system cost  
• Spread Spectrum clocking (down spread)  
• Enables ACPI-compliant designs  
• Power-down features (PCI_STOP#, CPU_STOP#  
PWR_DWN#)  
• Supports up to four CPU clock frequencies  
• Enables ATE and “bed of nails” testing  
• Widely available standard package enables lower cost  
• Three Select inputs (Mode select and IC Frequency  
Select)  
• OE and Test Mode support  
• 56-pin SSOP package and 56-pin TSSOP package  
Logic Block Diagram  
Pin Configurations  
SSOP and TSSOP  
Top View  
REF  
VDD_REF  
VDD_REF  
XTAL_IN  
XTAL_OUT  
GND_REF  
PCI_F0  
1
2
3
4
5
6
56  
55  
54  
53  
52  
51  
50  
X1  
X2  
XTAL  
OSC  
PWR  
REF  
S1  
S0  
PLL Ref Freq  
CPU_STOP#  
Divider  
Network  
CPU0  
PLL 1  
PCI_F1  
CPU#0  
VDD_CPU  
CPU1  
VDD_CPU  
CPU0:2  
Stop  
Clock  
Control  
PCI_F2  
7
PWR  
Gate  
S0:2  
PWR_GD#  
VDD_PCI  
GND_PCI  
PCI0  
49  
48  
47  
46  
8
CPU#0:2  
CPU#1  
9
CPU_STOP#  
GND_CPU  
VDD_CPU  
10  
11  
PCI1  
VDD_PCI  
PCI_F0:2  
PWR  
PCI2  
CPU2  
45  
44  
43  
42  
41  
12  
13  
Stop  
Clock  
Control  
PCI3  
CPU#2  
MULT0#  
PCI0:6  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
VDD_PCI  
GND_PCI  
PCI4  
IREF  
PCI_STOP#  
PWR_DWN#  
/2  
VDD_3V66  
3V66_0  
GND_IREF  
S2  
PWR  
40  
39  
38  
PCI5  
PCI6  
VDD_3V66  
3V66_2:4/  
USB  
66BUFF0:2  
PWR  
DOT  
3V66_5/ 66IN  
GND_3V66  
VDD_ 48 MHz  
37  
36  
35  
34  
66BUFF0/3V66_2  
66BUFF1/3V66_3  
GND_ 48 MHz  
3V66_1/VCH  
PCI_STOP#  
3V66_0  
VDD_48MHz  
USB (48MHz)  
PLL 2  
PWR  
66BUFF2/3V66_4  
66IN/3V66_5  
33  
32  
31  
30  
29  
24  
25  
DOT (48MHz)  
PWR_DWN#  
VDD_CORE  
GND_CORE  
VDD_3V66  
GND_3V66  
26  
27  
28  
VCH_CLK/ 3V66_1  
SCLK  
PWR_GD#  
SDATA  
SDATA  
SCLK  
SMBus  
Logic  
.......................Document #: 38-07010 Rev. *C Page 1 of 16  
400 West Cesar Chavez, Austin, TX 78701 1+(512) 416-8500 1+(512) 416-9669  
www.silabs.com  

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