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CYW312OXC

更新时间： 2024-01-21 16:01:05
品牌 Logo 应用领域
SPECTRALINEAR /
页数 文件大小 规格书
19页 193K
描述
FTG for VIA⑩ K7 Series Chipset with Programmable Output Frequency

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CYW312OXC 技术参数

是否Rohs认证： 符合生命周期：Transferred
零件包装代码：SSOP包装说明：SSOP, SSOP48,.4
针数：48Reach Compliance Code：compliant
ECCN代码：EAR99HTS代码：8542.39.00.01
风险等级：5.51Is Samacsys：N
其他特性：ALSO REQUIRES 2.5V SUPPLYJESD-30 代码：R-PDSO-G48
JESD-609代码：e4长度：15.875 mm
湿度敏感等级：3端子数量：48
最高工作温度：70 °C最低工作温度：
最大输出时钟频率：200 MHz封装主体材料：PLASTIC/EPOXY
封装代码：SSOP封装等效代码：SSOP48,.4
封装形状：RECTANGULAR封装形式：SMALL OUTLINE, SHRINK PITCH
峰值回流温度（摄氏度）：260电源：2.5/3.3 V
主时钟/晶体标称频率：14.31818 MHz认证状态：Not Qualified
座面最大高度：2.794 mm子类别：Clock Generators
最大供电电压：3.465 V最小供电电压：3.135 V
标称供电电压：3.3 V表面贴装：YES
技术：CMOS温度等级：COMMERCIAL
端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)端子形式：GULL WING
端子节距：0.635 mm端子位置：DUAL
处于峰值回流温度下的最长时间：20宽度：7.5057 mm
uPs/uCs/外围集成电路类型：CLOCK GENERATOR, PROCESSOR SPECIFICBase Number Matches：1

CYW312OXC 数据手册

 浏览型号CYW312OXC的Datasheet PDF文件第10页浏览型号CYW312OXC的Datasheet PDF文件第11页浏览型号CYW312OXC的Datasheet PDF文件第12页浏览型号CYW312OXC的Datasheet PDF文件第14页浏览型号CYW312OXC的Datasheet PDF文件第15页浏览型号CYW312OXC的Datasheet PDF文件第16页 
W312-02  
Table 6. Register Summary  
Name  
Description  
Pro_Freq_EN  
Programmable output frequencies enabled  
0 = Disabled (default)  
1 = Enabled  
When it is disabled, the operating output frequency will be determined by either the latched value of  
FS[4:0] inputs or the programmed value of SEL[4:0]. If FS_Override bit is clear, latched FS[4:0] inputs  
will be used. If FS_Override bit is set, programmed value of SEL[4:0] will be used.  
When it is enabled, the CPU output frequency will be determined by the programmed value of  
CPUFSEL_N, CPUFSEL_M and the PLL Gear Constant. The program value of FS_Override, SEL[4:0]  
or the latched value of FS[4:0] will determine the PLL Gear Constant and the frequency ratio between  
CPU and other frequency outputs  
FS_Override  
When Pro_Freq_EN is cleared or disabled,  
0 = Select operating frequency by FS input pins (default)  
1 = Select operating frequency by SEL bits in SMBus control bytes  
When Pro_Freq_EN is set or enabled,  
0 = Frequency output ratio between CPU and other frequency groups and the PLL Gear Constant are  
based on the latched value of FS input pins (default)  
1 = Frequency output ratio between CPU and other frequency groups and the PLL Gear Constant are  
based on the programmed value of SEL bits in SMBus control bytes  
CPU_FSEL_N,  
CPU_FSEL_M  
When Prog_Freq_EN is set or enabled, the values programmed in CPU_FSEL_N[7:0] and  
CPU_FSEL_M[6:0] determines the CPU output frequency. The new frequency will start to load  
whenever there is an update to either CPU_FSEL_N[7:0] or CPU_FSEL_M[6:0]. Therefore, it is recom-  
mended to use Word or Block write to update both registers within the same SMBus bus operation.  
The setting of FS_Override bit determines the frequency ratio for CPU, AGP and PIC. When  
FS_Override is cleared or disabled, the frequency ratio follows the latched value of the FS input pins.  
When FS_Override is set or enabled, the frequency ratio follows the programmed value of SEL bits in  
SMBus control bytes.  
ROCV_FREQ_SEL  
ROCV_FREQ_SEL determines the source of the recover frequency when a Watchdog timer time-out  
occurs. The clock generator will automatically switch to the recovery CPU frequency based on the  
selection on ROCV_FREQ_SEL.  
0 = From latched FS[4:0]  
1 = From the settings of ROCV_FREQ_N[7:0] & ROCV_FREQ_M[6:0]  
ROCV_FREQ_N[7:0], When ROCV_FREQ_SEL is set, the values programmed in ROCV_FREQ_N[7:0] and  
ROCV_FREQ_M[6:0] ROCV_FREQ_M[6:0] will be used to determine the recovery CPU output frequency when a  
Watchdog timer time-out occurs  
The setting of FS_Override bit determines the frequency ratio for CPU, AGP and PIC. When it is cleared,  
the same frequency ratio stated in the Latched FS[4:0] register will be used.  
When it is set, the frequency ratio stated in the SEL[4:0] register will be used.  
The new frequency will start to load whenever there is an update to either ROCV_FREQ_N[7:0] and  
ROCV_FREQ_M[6:0]. Therefore, it is recommended to use Word or Block write to update both registers  
within the same SMBus bus operation.  
WD_EN  
0 = Stop and reload Watchdog timer  
1 = Enable Watchdog timer. It will start counting down after a frequency change occurs.  
WD_TO_STATUS  
Watchdog Timer Time-out Status bit  
0 = No time-out occurs (READ); Ignore (WRITE)  
1 = time-out occurred (READ); Clear WD_TO_STATUS (WRITE)  
WD_TIMER[4:0]  
These bits store the time-out value of the Watchdog timer. The scale of the timer is determine by the  
prescaler.  
The timer can support a value of 150 ms to 4.8 sec when the pre-scaler is set to 150 ms. If the pre-scaler  
is set to 2.5 sec, it can support a value from 2.5 sec to 80 sec.  
When the Watchdog timer reaches “0”, it will set the WD_TO_STATUS bit.  
WD_PRE_SCALER  
0 = 150 ms  
1 = 2.5 sec  
Rev 1.0,November 27, 2006  
Page 13 of 19  
1...10111213141516...19

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