5秒后页面跳转
CYW255OXC PDF预览

CYW255OXC

更新时间: 2024-02-25 17:43:32
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 逻辑集成电路光电二极管驱动动态存储器双倍数据速率
页数 文件大小 规格书
10页 256K
描述
200-MHz 24-Output Buffer for 4 DDR or 3 SDRAM DIMMS

CYW255OXC 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:SSOP
包装说明:SSOP,针数:48
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.3其他特性:ALSO OPERATES AT 3.3V SUPPLY
系列:255输入调节:STANDARD
JESD-30 代码:R-PDSO-G48长度:15.875 mm
逻辑集成电路类型:LOW SKEW CLOCK DRIVER功能数量:1
反相输出次数:端子数量:48
实输出次数:24最高工作温度:70 °C
最低工作温度:封装主体材料:PLASTIC/EPOXY
封装代码:SSOP封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, SHRINK PITCH峰值回流温度(摄氏度):NOT SPECIFIED
传播延迟(tpd):10 ns认证状态:Not Qualified
Same Edge Skew-Max(tskwd):0.15 ns座面最大高度:2.794 mm
最大供电电压 (Vsup):2.625 V最小供电电压 (Vsup):2.375 V
标称供电电压 (Vsup):2.5 V表面贴装:YES
温度等级:COMMERCIAL端子形式:GULL WING
端子节距:0.635 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:7.5057 mm
Base Number Matches:1

CYW255OXC 数据手册

 浏览型号CYW255OXC的Datasheet PDF文件第2页浏览型号CYW255OXC的Datasheet PDF文件第3页浏览型号CYW255OXC的Datasheet PDF文件第4页浏览型号CYW255OXC的Datasheet PDF文件第5页浏览型号CYW255OXC的Datasheet PDF文件第6页浏览型号CYW255OXC的Datasheet PDF文件第7页 
W255  
200-MHz 24-Output Buffer for 4 DDR  
or 3 SDRAM DIMMS  
Features  
Functional Description  
• One input to 24-output buffer/driver  
• Supports up to 4 DDR DIMMs or 3 SDRAM DIMMS  
• One additional output for feedback  
• SMBus interface for individual output control  
• Low skew outputs (< 100 ps)  
• Supports 266-, 333-, and 400-MHz DDR SDRAM  
• Dedicated pin for power management support  
• Space-saving 48-pin SSOP package  
The W255 is a 3.3V/2.5V buffer designed to distribute  
high-speed clocks in PC applications. The part has 24 outputs.  
Designers can configure these outputs to support four unbuf-  
fered DDR DIMMS or to support three unbuffered standard  
SDRAM DIMMs and two DDR DIMMS. The W255 can be used  
in conjunction with the W250 or similar clock synthesizer for  
the VIA Pro 266 chipset.  
The W255 also includes an SMBus interface which can enable  
or disable each output clock. On power-up, all output clocks  
are enabled (internal pull up).  
Block Diagram  
Pin Configuration[1]  
FBOUT  
DDR0T_SDRAM10  
DDR0C_SDRAM11  
SSOP  
Top View  
BUF_IN  
1
2
3
4
5
6
7
8
FBOUT  
VDD3.3_2.5  
48  
47  
SEL_DDR*  
VDD2.5  
GND  
DDR1T_SDRAM0  
DDR1C_SDRAM1  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
28  
27  
26  
25  
GND  
DDR2T_SDRAM2  
DDR0T_SDRAM10  
DDR11T  
DDR11C  
DDR10T  
DDR10C  
VDD2.5  
GND  
DDR2C_SDRAM3 DDR0C_SDRAM11  
DRR1T_SDRAM0  
DDR3T_SDRAM4  
DDR1C_SDRAM1  
DDR3C_SDRAM5  
SDATA  
VDD3.3_2.5  
DDR4T_SDRAM6  
DDR4C_SDRAM7  
9
SMBus  
GND  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
DDR2T_SDRAM2  
DDR9T  
DDR9C  
VDD2.5  
PWR_DWN#*  
GND  
DDR8T  
DDR8C  
VDD2.5  
GND  
Decoding  
DDR5T_SDRAM8  
DDR2C_SDRAM3  
SCLOCK  
DDR5C_SDRAM9  
VDD3.3_2.5  
BUF_IN  
DDR6T  
GND  
DDR6C  
DDR3T_SDRAM4  
DDR7T  
DDR3C_SDRAM5  
DDR7C  
VDD3.3_2.5  
DDR8T  
DDR8C  
DDR9T  
GND  
DDR4T_SDRAM6  
DDR7T  
DDR7C  
DDR6T  
DDR6C  
GND  
DDR4C_SDRAM7  
DDR5T_SDRAM8  
DDR9C  
DDR5C_SDRAM9  
DDR10T  
DDR10C  
VDD3.3_2.5  
Power Down Control  
PWR_DWN#  
SEL_DDR  
SDATA  
SCLK  
Note:  
DDR11T  
1. Internal 100K pull-up resistors present on inputs marked  
with *. Design should not rely solely on internal pull-up resistor  
to set I/O pins HIGH.  
DDR11C  
Cypress Semiconductor Corporation  
3901 North First Street  
San Jose, CA 95134  
408-943-2600  
Document #: 38-07255 Rev. *D  
Revised April 28, 2005  

与CYW255OXC相关器件

型号 品牌 描述 获取价格 数据表
CYW255OXCT SPECTRALINEAR 200 MHz 24-Output Buffer for 4 DDR or 3 SDRAM DIMMS

获取价格

CYW255OXCT CYPRESS 200-MHz 24-Output Buffer for 4 DDR or 3 SDRAM DIMMS

获取价格

CYW256OXC SPECTRALINEAR 12 Output Buffer for 2 DDR and 3 SRAM DIMMS

获取价格

CYW256OXC CYPRESS 12 Output Buffer for 2 DDR and 3 SRAM DIMMS

获取价格

CYW256OXCT CYPRESS 12 Output Buffer for 2 DDR and 3 SRAM DIMMS

获取价格

CYW256OXCT SPECTRALINEAR 12 Output Buffer for 2 DDR and 3 SRAM DIMMS

获取价格