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CYW256OXCT PDF预览

CYW256OXCT

更新时间: 2024-11-27 22:08:47
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 逻辑集成电路静态存储器光电二极管驱动双倍数据速率
页数 文件大小 规格书
9页 177K
描述
12 Output Buffer for 2 DDR and 3 SRAM DIMMS

CYW256OXCT 数据手册

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W256  
12 Output Buffer for 2 DDR and 3 SRAM DIMMS  
Features  
Functional Description  
• One input to 12 output buffer/drivers  
• Supports up to 2 DDR DIMMs or 3 SDRAM DIMMS  
• One additional output for feedback  
The W256 is a 3.3V/2.5V buffer designed to distribute  
high-speed clocks in PC applications. The part has 12 outputs.  
Designers can configure these outputs to support 3 unbuffered  
standard SDRAM DIMMs and 2 DDR DIMMs. The W256 can  
be used in conjunction with the W250-02 or similar clock  
synthesizer for the VIA Pro 266 chipset.  
• SMBus interface for individual output control  
• Low skew outputs (< 100 ps)  
The W256 also includes an SMBus interface which can enable  
or disable each output clock. On power-up, all output clocks  
are enabled (internal pull-up).  
• Supports 266 MHz and 333 MHz DDR SDRAM  
• Dedicated pin for power management support  
• Space-saving 28-pin SSOP package  
Block Diagram  
Pin Configuration[1]  
VDD3.5_2.5  
FBOUT  
BUF_IN  
SSOP  
Top View  
DDR0T_SDRAM0  
DDR0C_SDRAM1  
FBOUT  
*PWR_DWN#  
DDR0T_SDRAM0  
DDR0C_SDRAM1  
VDD3.3_2.5  
1
2
3
4
5
6
7
8
28  
27  
26  
25  
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
SEL_DDR*  
DDR5T_SDRAM10  
DDR5C_SDRAM11  
VDD3.3_2.5  
GND  
DDR4T_SDRAM8  
DDR4C_SDRAM9  
VDD3.3_2.5  
GND  
DDR3T_SDRAM6  
DDR3C_SDRAM7  
GND  
SCLK  
SDATA  
DDR1T_SDRAM2  
DDR1C_SDRAM3  
GND  
SMBus  
Decoding  
SDATA  
DDR1T_SDRAM2  
DDR1C_SDRAM3  
VDD3.3_2.5  
BUF_IN  
GND  
DDR2T_SDRAM4  
DDR2C_SDRAM5  
VDD3.3_2.5  
&
DDR2T_SDRAM4  
DDR2C_SDRAM5  
SCLOCK  
9
Powerdown  
Control  
10  
11  
12  
13  
14  
PWR_DWN#  
DDR3T_SDRAM6  
DDR3C_SDRAM7  
DDR4T_SDRAM8  
DDR4C_SDRAM9  
DDR5T_SDRAM10  
DDR5C_SDRAM11  
SEL_DDR  
Note:  
1. Internal 100K pull-up resistors present on inputs marked with *. Design should not rely solely on internal pull-up resistor to set I/O pins HIGH.  
Cypress Semiconductor Corporation  
Document #: 38-07256 Rev. *C  
3901 North First Street  
San Jose, CA 95134  
408-943-2600  
Revised August 30, 2004  

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