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CYW312OXC

更新时间： 2024-11-28 03:27:47
品牌 Logo 应用领域
赛普拉斯 - CYPRESS /
页数 文件大小 规格书
20页 254K
描述
FTG for VIA⑩ K7 Series Chipset with Programmable Output Frequency

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CYW312OXC 数据手册

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W312-02  
FTG for VIA™ K7 Series Chipset with  
Programmable Output Frequency  
• Low jitter and tightly controlled clock skew  
• Two pairs of differential CPU clocks  
Features  
• Single chip FTG solution for VIA™ K7 Series chipsets  
• Programmable clock output frequency with less than  
• Eleven copies of PCI clocks  
• Three copies of 66-MHz outputs  
1 MHz increment  
• Two copies of 48-MHz outputs  
• Integrated fail-safe Watchdog timer for system  
recovery  
• Automatically switch to HW selected or SW  
programmed clock frequency when watchdog timer  
time-out  
• Three copies of 14.31818-MHz reference clocks  
• One RESET output for system recovery  
• Power management control support  
• Capable of generate system RESET after a watchdog  
timer time-out occurs or a change in output frequency  
via SMBus interface  
Key Specifications  
CPU Outputs Cycle-to-cycle Jitter: .............................250 ps  
• Support SMBus byte read/write and block read/ write  
48-MHz, 3V66, PCI Outputs  
operations to simplify system BIOS development  
Cycle-to-cycle Jitter:....................................................500 ps  
• Vendor ID and Revision ID support  
• Programmable drive strength for PCI output clocks  
• ProgrammableoutputskewbetweenCPU,AGPandPCI  
CPU, 3V66 Output Skew:............................................200 ps  
48-MHz Output Skew: .................................................250 ps  
PCI Output Skew:........................................................500 ps  
• Maximized EMI suppression using Cypress’s Spread  
Spectrum technology  
Block Diagram  
Pin Configuration[1]  
VDD_REF  
REF2  
VDD_REF  
GND_REF  
X1  
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
28  
27  
26  
25  
REF0/FS0*  
REF1/FS1*  
REF2  
1
2
X1  
X2  
3
XTAL  
OSC  
REF1/FS1*  
REF0/FS0*  
X2  
REF_STOP#*  
AGP_STOP#*  
GND_CPU  
CPUT0  
4
VDD_48MHz  
*FS2/48MHz  
*FS3/24_48MHz  
GND_48MHz  
*FS4/PCI_F  
*SEL24_48#/PCI0  
PCI1  
5
PLL REF FREQ  
VDD_CPU  
6
7
CPUT0,CPUC0  
CPUT_CS,CPUC_CS  
VDD_AGP  
Divider,  
Delay,  
and  
8
CPUC0  
2
SDATA  
SCLK  
SMBus  
Logic  
VDD_CPU  
CPUT_CS  
CPUC_CS  
GND_CPU  
CPU_STOP#*  
PCI_STOP#*  
PD#*  
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
Phase  
Control  
Logic  
AGP0:2  
GND_PCI  
PCI2  
3
(FS0:4)  
PCI3  
VDD_PCI  
PCI4  
VDD_PCI  
VDD_CORE  
GND_CORE  
SDATA  
PCI0/SEL24_48#*  
PCI5  
PLL 1  
PCI1:8  
PCI6  
5
GND_PCI  
PCI7  
SCLK  
PD#  
CPU_STOP#  
PCI_STOP#  
AGP_STOP#  
REF_STOP#  
GND_AGP  
AGP2  
PCI9_E  
PCI8  
PCI9_E  
AGP1  
VDD_PCI  
RST#  
AGP0  
RST#  
VDD_AGP  
VDD_48MHz  
48MHz/FS3*  
Note:  
1. Internal 100K pull-up resistors present on inputs marked with *. De-  
sign should not rely solely on internal pull-up resistor to set I/O pins  
HIGH.  
PLL2  
24_48MHz/FS4*  
/2  
SEL24_48#*  
Cypress Semiconductor Corporation  
•
3901 North First Street  
•
San Jose, CA 95134  
•
408-943-2600  
Document #: 38-07259 Rev. *C  
Revised April 28, 2005  
1234567...20

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