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CYW311OXC PDF预览

CYW311OXC

更新时间: 2024-02-12 03:57:36
品牌 Logo 应用领域
SPECTRALINEAR 双倍数据速率
页数 文件大小 规格书
18页 250K
描述
FTG for VIA⑩ Pro-266 DDR Chipset

CYW311OXC 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:SSOP
包装说明:SSOP,针数:48
Reach Compliance Code:unknownECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.48
其他特性:CAN ALSO OPERATE AT 3.3V SUPPLYJESD-30 代码:R-PDSO-G48
长度:15.875 mm端子数量:48
最高工作温度:70 °C最低工作温度:
最大输出时钟频率:200 MHz封装主体材料:PLASTIC/EPOXY
封装代码:SSOP封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, SHRINK PITCH峰值回流温度(摄氏度):NOT SPECIFIED
主时钟/晶体标称频率:14.31818 MHz认证状态:Not Qualified
座面最大高度:2.794 mm最大供电电压:2.625 V
最小供电电压:2.375 V标称供电电压:2.5 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子形式:GULL WING
端子节距:0.635 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:7.5057 mm
uPs/uCs/外围集成电路类型:CLOCK GENERATOR, PROCESSOR SPECIFICBase Number Matches:1

CYW311OXC 数据手册

 浏览型号CYW311OXC的Datasheet PDF文件第2页浏览型号CYW311OXC的Datasheet PDF文件第3页浏览型号CYW311OXC的Datasheet PDF文件第4页浏览型号CYW311OXC的Datasheet PDF文件第5页浏览型号CYW311OXC的Datasheet PDF文件第6页浏览型号CYW311OXC的Datasheet PDF文件第7页 
W311  
FTG for VIA™ Pro-266 DDR Chipset  
• Supports Intel® Celeron® and Pentium® III class  
processor  
Features  
• Maximized EMI Suppression using Cypress’s Spread  
Spectrum Technology  
• Three copies of CPU output  
• Nine copies of PCI output  
• System frequency synthesizer for VIA Pro-2000  
• One 48 MHz output for USB  
• Programmable clock output frequency with less than 1  
MHz increment  
• One 24 MHz or 48 MHz output for SIO  
• Two buffered reference outputs  
• Three copies of APIC output  
• Supports frequencies up to 200MHz  
• SMBus Interface for programming  
• Power management control inputs  
• Available in 48-pin SSOP  
• Integrated fail-safe Watchdog Timer for system  
recovery  
• Automatically switch to HW selected or SW  
programmed clock frequency when Watchdog Timer  
time-out  
• Capable of generate system RESET after a Watchdog  
Timer time-out occurs or a change in output frequency  
via SMBus interface  
Key Specifications  
• Support SMBus byte read/write and block read/ write  
operations to simplify system BIOS development  
CPU Cycle-to-cycle Jitter: ..........................................250 ps  
CPU to CPU Output Skew...........................................175 ps  
PCI Cycle-to-cycle Jitter:.............................................500 ps  
PCI to PCI Output Skew:.............................................500 ps  
• Vendor ID and Revision ID support  
• Programmable drive strength for CPU and PCI output  
clocks  
• ProgrammableoutputskewbetweenCPU, AGPandPCI  
Block Diagram  
Pin Configuration[1]  
Note:  
1. Signals marked with * have internal pull-up resistors  
Rev 1.0, November 25, 2006  
Page 1 of 18  
2200 Laurelwood Road, Santa Clara, CA 95054  
Tel:(408) 855-0555 Fax:(408) 855-0550  
www.SpectraLinear.com  

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