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CYW256OXCT PDF预览

CYW256OXCT

更新时间: 2024-02-12 07:10:42
品牌 Logo 应用领域
SPECTRALINEAR 逻辑集成电路静态存储器光电二极管驱动双倍数据速率
页数 文件大小 规格书
7页 141K
描述
12 Output Buffer for 2 DDR and 3 SRAM DIMMS

CYW256OXCT 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:SSOP包装说明:SSOP,
针数:28Reach Compliance Code:unknown
HTS代码:8542.39.00.01风险等级:5.62
其他特性:ALSO OPERATES AT 3.3V系列:256
输入调节:STANDARDJESD-30 代码:R-PDSO-G28
长度:10.2 mm逻辑集成电路类型:LOW SKEW CLOCK DRIVER
功能数量:1反相输出次数:
端子数量:28实输出次数:12
最高工作温度:70 °C最低工作温度:
封装主体材料:PLASTIC/EPOXY封装代码:SSOP
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, SHRINK PITCH
峰值回流温度(摄氏度):NOT SPECIFIED传播延迟(tpd):10 ns
认证状态:Not QualifiedSame Edge Skew-Max(tskwd):0.15 ns
座面最大高度:2 mm最大供电电压 (Vsup):2.625 V
最小供电电压 (Vsup):2.375 V标称供电电压 (Vsup):2.5 V
表面贴装:YES温度等级:COMMERCIAL
端子形式:GULL WING端子节距:0.65 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:5.3 mm最小 fmax:66 MHz
Base Number Matches:1

CYW256OXCT 数据手册

 浏览型号CYW256OXCT的Datasheet PDF文件第2页浏览型号CYW256OXCT的Datasheet PDF文件第3页浏览型号CYW256OXCT的Datasheet PDF文件第4页浏览型号CYW256OXCT的Datasheet PDF文件第5页浏览型号CYW256OXCT的Datasheet PDF文件第6页浏览型号CYW256OXCT的Datasheet PDF文件第7页 
W256  
12 Output Buffer for 2 DDR and 3 SRAM DIMMS  
Functional Description  
Features  
• One input to 12 output buffer/drivers  
• Supports up to 2 DDR DIMMs or 3 SDRAM DIMMS  
• One additional output for feedback  
The W256 is a 3.3V/2.5V buffer designed to distribute  
high-speed clocks in PC applications. The part has 12 outputs.  
Designers can configure these outputs to support 3 unbuffered  
standard SDRAM DIMMs and 2 DDR DIMMs. The W256 can  
be used in conjunction with the W250-02 or similar clock  
synthesizer for the VIA Pro 266 chipset.  
• SMBus interface for individual output control  
• Low skew outputs (< 100 ps)  
The W256 also includes an SMBus interface which can enable  
or disable each output clock. On power-up, all output clocks  
are enabled (internal pull-up).  
• Supports 266 MHz and 333 MHz DDR SDRAM  
• Dedicated pin for power management support  
• Space-saving 28-pin SSOP package  
Block Diagram  
Pin Configuration[1]  
VDD3.5_2.5  
FBOUT  
BUF_IN  
SSOP  
Top View  
DDR0T_SDRAM0  
DDR0C_SDRAM1  
FBOUT  
*PWR_DWN#  
DDR0T_SDRAM0  
DDR0C_SDRAM1  
VDD3.3_2.5  
1
2
3
4
5
6
28  
27  
26  
25  
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
SEL_DDR*  
DDR5T_SDRAM10  
DDR5C_SDRAM11  
VDD3.3_2.5  
GND  
DDR4T_SDRAM8  
DDR4C_SDRAM9  
VDD3.3_2.5  
GND  
DDR3T_SDRAM6  
DDR3C_SDRAM7  
GND  
SCLK  
SDATA  
DDR1T_SDRAM2  
DDR1C_SDRAM3  
GND  
SMBus  
SDATA  
DDR1T_SDRAM2  
DDR1C_SDRAM3  
VDD3.3_2.5  
BUF_IN  
GND  
DDR2T_SDRAM4  
DDR2C_SDRAM5  
VDD3.3_2.5  
7
8
9
10  
11  
12  
13  
14  
Decoding  
&
DDR2T_SDRAM4  
DDR2C_SDRAM5  
SCLOCK  
Powerdown  
Control  
PWR_DWN#  
DDR3T_SDRAM6  
DDR3C_SDRAM7  
DDR4T_SDRAM8  
DDR4C_SDRAM9  
DDR5T_SDRAM10  
DDR5C_SDRAM11  
SEL_DDR  
Note:  
1. Internal 100K pull-up resistors present on inputs marked with *. Design should not rely solely on internal pull-up resistor to set I/O pins HIGH.  
Rev 1.0, November 25, 2006  
Page 1 of 7  
www.SpectraLinear.com  
2200 Laurelwood Road, Santa Clara, CA 95054  
Tel:(408) 855-0555 Fax:(408) 855-0550  

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