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CYW2336ZIT

更新时间: 2024-11-09 20:38:39
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 光电二极管
页数 文件大小 规格书
11页 169K
描述
PLL/Frequency Synthesis Circuit, PDSO20

CYW2336ZIT 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
Reach Compliance Code:not_compliant风险等级:5.92
JESD-30 代码:R-PDSO-G20JESD-609代码:e0
端子数量:20最高工作温度:85 °C
最低工作温度:-40 °C封装主体材料:PLASTIC/EPOXY
封装代码:TSSOP封装等效代码:TSSOP20,.25
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
电源:3/5 V认证状态:Not Qualified
子类别:PLL or Frequency Synthesis Circuits表面贴装:YES
温度等级:INDUSTRIAL端子面层:Tin/Lead (Sn/Pb)
端子形式:GULL WING端子节距:0.635 mm
端子位置:DUALBase Number Matches:1

CYW2336ZIT 数据手册

 浏览型号CYW2336ZIT的Datasheet PDF文件第2页浏览型号CYW2336ZIT的Datasheet PDF文件第3页浏览型号CYW2336ZIT的Datasheet PDF文件第4页浏览型号CYW2336ZIT的Datasheet PDF文件第5页浏览型号CYW2336ZIT的Datasheet PDF文件第6页浏览型号CYW2336ZIT的Datasheet PDF文件第7页 
CYW2336  
Dual Serial Input PLL with 2.0- and 1.1-GHz Prescalers  
Features  
Applications  
• Operating voltage 2.7V to 5.5V  
• Operating frequency to 2.0 GHz on PLL1 and 1.1 GHz  
on PLL2 with prescaler ratios of 64/65 and 128/129  
The Cypress CYW2336 is a dual serial input PLL frequency  
synthesizer designed for high-volume, low-cost wireless com-  
munications applications. One 2.0-GHz and one 1.1-GHz  
prescaler, each with pulse swallow capability are included. The  
device operates from 2.7V and dissipates only 24 mW.  
• Lock detect feature  
µA typical at 3.0V  
• Power-down mode I < 1  
CC  
• Serial data input accepts data clock rates as low as  
1 kHz  
• Low power/voltage operation with low current standby  
mode  
• On-chip reference oscillator  
• Available in a 20-pin TSSOP (Thin Shrink Small Outline  
Package)  
Dual PLL Block Diagram  
GND  
GND  
VCC  
V
VP1  
(4)  
(1)  
(7)  
CC (20)  
(2)  
(5)  
(3)  
DOPLL1  
Prescaler  
64/65 or  
128/129  
FIN  
1
fp1  
Binary 7-Bit  
Swallow Counter  
Binary 11-Bit  
Programmable Counter  
Phase  
Detector  
Charge  
Pump  
(6)  
FIN1#  
19-Bit  
Latch  
Pwr-dwn  
PLL1  
(8)  
OSC_IN  
fr1  
fr2  
15-Bit  
fr fp  
Reference Counter  
(10)  
FO/LD  
OSC_OUT  
Monitor  
Output  
Selector  
(9)  
20-Bit Latch  
Latch  
Selector  
(13)  
LE  
20-Bit Latch  
(12)  
DATA  
Power  
Control  
15-Bit  
22-Bit  
Reference Counter  
Cntrl  
Shift  
Reg.  
(11)  
CLOCK  
19-Bit  
Latch  
Pwr-dwn  
PLL2  
(16)  
Phase  
Detector  
Charge  
Pump  
(18)  
FIN2  
Prescaler  
64/65 or  
128/129  
Binary 7-Bit  
Swallow Counter  
Binary 11-Bit  
Programmable Counter  
DOPLL2  
(15)  
IN2#  
fp2  
F
(14)  
(19)  
(17)  
GND  
GND  
VP2  
Pin Configuration  
VCC  
1
1
2
20  
19  
18  
17  
16  
15  
14  
13  
12  
11  
VCC  
VP2  
2
VP1  
DOPLL1  
GND  
3
DOPLL2  
GND  
4
FIN  
1
5
FIN2  
FIN1#  
GND  
6
FIN2#  
GND  
LE  
7
OSC_IN  
OSC_OUT  
FO/LD  
8
9
DATA  
CLOCK  
10  
Cypress Semiconductor Corporation  
3901 North First Street  
San Jose  
CA 95134  
408-943-2600  
September 8, 2000, rev. *A  

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