Datasheet > CYW2336ZIT

CYW2336ZIT

更新时间： 2024-01-08 21:50:12

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		光电二极管
页数	文件大小	规格书
11页	169K
描述
PLL/Frequency Synthesis Circuit, PDSO20

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技术参数
数据手册

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CYW2336ZIT 技术参数

是否Rohs认证：	不符合	生命周期：	Obsolete
Reach Compliance Code：	not_compliant	风险等级：	5.92
JESD-30 代码：	R-PDSO-G20	JESD-609代码：	e0
端子数量：	20	最高工作温度：	85 °C
最低工作温度：	-40 °C	封装主体材料：	PLASTIC/EPOXY
封装代码：	TSSOP	封装等效代码：	TSSOP20,.25
封装形状：	RECTANGULAR	封装形式：	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
电源：	3/5 V	认证状态：	Not Qualified
子类别：	PLL or Frequency Synthesis Circuits	表面贴装：	YES
温度等级：	INDUSTRIAL	端子面层：	Tin/Lead (Sn/Pb)
端子形式：	GULL WING	端子节距：	0.635 mm
端子位置：	DUAL	Base Number Matches：	1

CYW2336ZIT 数据手册

CYW2336

Dual Serial Input PLL with 2.0- and 1.1-GHz Prescalers

Features

Applications

• Operating voltage 2.7V to 5.5V

• Operating frequency to 2.0 GHz on PLL1 and 1.1 GHz

on PLL2 with prescaler ratios of 64/65 and 128/129

The Cypress CYW2336 is a dual serial input PLL frequency

synthesizer designed for high-volume, low-cost wireless com-

munications applications. One 2.0-GHz and one 1.1-GHz

prescaler, each with pulse swallow capability are included. The

device operates from 2.7V and dissipates only 24 mW.

• Lock detect feature

µA typical at 3.0V

• Power-down mode I < 1

• Serial data input accepts data clock rates as low as

1 kHz

• Low power/voltage operation with low current standby

mode

• On-chip reference oscillator

• Available in a 20-pin TSSOP (Thin Shrink Small Outline

Package)

Dual PLL Block Diagram

GND

V_CC

VP1

(4)

(1)

(7)

_CC(20)

(2)

(5)

(3)

D_OPLL1

Prescaler

64/65 or

128/129

F_IN

fp1

Binary 7-Bit

Swallow Counter

Binary 11-Bit

Programmable Counter

Phase

Detector

Charge

Pump

(6)

F_IN1#

19-Bit

Latch

Pwr-dwn

PLL1

(8)

OSC_IN

fr1

fr2

15-Bit

fr fp

Reference Counter

(10)

F_O/LD

OSC_OUT

Monitor

Output

Selector

(9)

20-Bit Latch

Latch

Selector

(13)

20-Bit Latch

(12)

DATA

Power

Control

15-Bit

22-Bit

Reference Counter

Cntrl

Shift

Reg.

(11)

CLOCK

19-Bit

Latch

Pwr-dwn

PLL2

(16)

Phase

Detector

Charge

Pump

(18)

F_IN2

Prescaler

64/65 or

128/129

Binary 7-Bit

Swallow Counter

Binary 11-Bit

Programmable Counter

D_OPLL2

(15)

_IN2#

fp2

(14)

(19)

(17)

GND

VP2

Pin Configuration

V_CC

V_P2

V_P1

D_OPLL1

GND

D_OPLL2

GND

F_IN

F_IN2

F_IN1#

GND

F_IN2#

GND

OSC_IN

OSC_OUT

F_O/LD

DATA

CLOCK

Cypress Semiconductor Corporation

•

3901 North First Street

•

San Jose

•

CA 95134

•

408-943-2600

September 8, 2000, rev. *A

12 3 4 5 6 7...11

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