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CYW2331LFI PDF预览

CYW2331LFI

更新时间: 2024-11-29 13:07:15
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 预分频器
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12页 251K
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CYW2331LFI 数据手册

 浏览型号CYW2331LFI的Datasheet PDF文件第2页浏览型号CYW2331LFI的Datasheet PDF文件第3页浏览型号CYW2331LFI的Datasheet PDF文件第4页浏览型号CYW2331LFI的Datasheet PDF文件第5页浏览型号CYW2331LFI的Datasheet PDF文件第6页浏览型号CYW2331LFI的Datasheet PDF文件第7页 
1CYW2331  
PRELIMINARY  
CYW2331  
Dual Serial Input PLL with 2.0-GHz and 600-MHz Prescalers  
Features  
Applications  
• Operating voltage: 2.7V to 5.5V  
• PLL1 operating frequency:  
— 2.0 GHz with prescaler ratios of 64/65 and 128/129  
• PLL2 operating frequency:  
— 600 MHz with prescaler ratios of 8/9 and 16/17  
• Lock detect feature  
The Cypress CYW2331 is a dual serial input PLL frequency  
synthesizer which includes a 2.0-GHz RF and a 600-MHz IF  
dual modulus prescaler to combine the RF and IF mixer fre-  
quency sections of wireless communication systems. The syn-  
thesizer is designed for cordless/cellular telephone systems,  
cable TV tuners, WLANs and other wireless communication  
systems. The device operates from 2.7V and dissipates only  
24 mW.  
• Available in a 20-pin TSSOP (Thin Shrink Small Outline  
Package)  
• Available in a 24-pin CSP (Chip Scale Package)  
• Available in a 20-pin MLF  
(Mirco Lead Frame Package)  
CYW2331 Dual Hi-Lo PLL Block Diagram  
GND (4)  
GND (7)  
VCC1 (1)  
VCC2 (20)  
VP1 (2)  
FIN1 (5)  
Prescaler  
64/65 or  
128/129  
fp1  
Binary 7-Bit  
Swallow Counter  
Binary 11-Bit  
Programmable Counter  
DOPLL1 (3)  
Phase  
Detector  
Charge  
Pump  
FIN1# (6)  
19-Bit  
Latch  
Pwr-dwn  
PLL1  
OSC_IN (8)  
fr fp  
fr1  
fr2  
15-Bit  
Monitor  
Output  
Selector  
Reference Counter  
FO/LD (10)  
20-Bit Latch  
Latch  
Selector  
LE (13)  
DATA (12)  
20-Bit Latch  
Power  
Control  
15-Bit  
Reference Counter  
22-Bit  
Shift  
Cntrl  
Reg.  
CLOCK (11)  
19-Bit  
Latch  
Pwr-dwn  
PLL2  
Phase  
Detector  
Charge  
Pump  
FIN2 (16)  
Prescaler  
8/9 or  
16/17  
Binary 4-Bit  
Swallow Counter  
Binary 11-Bit  
Programmable Counter  
DOPLL2 (18)  
fp2  
FIN2# (15)  
GND (14)  
GND (9)  
GND (17)  
VP2 (19)  
Pin Configuration  
V
1
1
2
20  
V
2
CC  
CC  
21  
20  
1
2
3
4
5
6
7
8
9
NC  
NC  
Vp1  
V 1  
19  
18  
17  
16  
15  
14  
13  
12  
11  
V 2  
P
P
DoPLL2  
GND  
Fin2  
D PLL1  
3
D PLL2  
O
O
19  
18  
17  
16  
15  
14  
13  
DoPLL1  
GND  
1
15  
DoPLL1  
GND  
GND  
4
GND  
2
3
4
5
GND  
Fin1  
14  
13  
12  
11  
Fin2  
Fin2#  
GND  
LE  
(Top View)  
Fin2#  
GND  
LE  
Fin1  
F
1
5
F
F
2
(Top View)  
IN  
IN  
IN  
Fin1#  
GND  
Fin1#  
GND  
F
1#  
6
2#  
IN  
GND  
OSC_IN  
GND  
7
GND  
LE  
DATA  
NC  
OSC_IN  
NC  
8
9
DATA  
CLOCK  
F /LD  
10  
O
MLF  
TSSOP  
CSP  
Cypress Semiconductor Corporation  
3901 North First Street  
San Jose  
CA 95134  
408-943-2600  
February 12, 2001. Rev. **  

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