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CYW2325ZITR PDF预览

CYW2325ZITR

更新时间: 2024-11-28 14:48:47
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 时钟光电二极管逻辑集成电路
页数 文件大小 规格书
11页 206K
描述
Prescaler, 1-Func, PDSO20, 0.173 INCH, MO-153AD, TSSOP-20

CYW2325ZITR 技术参数

是否Rohs认证:不符合生命周期:Obsolete
零件包装代码:TSSOP包装说明:0.173 INCH, MO-153AD, TSSOP-20
针数:20Reach Compliance Code:compliant
HTS代码:8542.39.00.01风险等级:5.92
Is Samacsys:N其他特性:64/65 DIVISION RATIO ALSO AVAILABLE
JESD-30 代码:R-PDSO-G20JESD-609代码:e0
长度:6.5 mm逻辑集成电路类型:PRESCALER
湿度敏感等级:1数据/时钟输入次数:1
功能数量:1端子数量:20
最高工作温度:85 °C最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY封装代码:TSSOP
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度(摄氏度):NOT SPECIFIED认证状态:Not Qualified
座面最大高度:1.1 mm最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):2.7 V标称供电电压 (Vsup):3 V
表面贴装:YES温度等级:INDUSTRIAL
端子面层:Tin/Lead (Sn/Pb)端子形式:GULL WING
端子节距:0.65 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:4.4 mm
最小 fmax:2500 MHzBase Number Matches:1

CYW2325ZITR 数据手册

 浏览型号CYW2325ZITR的Datasheet PDF文件第2页浏览型号CYW2325ZITR的Datasheet PDF文件第3页浏览型号CYW2325ZITR的Datasheet PDF文件第4页浏览型号CYW2325ZITR的Datasheet PDF文件第5页浏览型号CYW2325ZITR的Datasheet PDF文件第6页浏览型号CYW2325ZITR的Datasheet PDF文件第7页 
25  
CYW2325  
Serial Input PLL with 2.5-GHz Prescaler  
Features  
Applications  
• Operating voltage 2.7V to 5.5V  
The CYW2325 is a serial-input high-performance frequency  
synthesizer which includes a dual modulus prescaler for RF  
applications up to 2.5 GHz. The synthesizer is designed for  
cellular telephone systems, portable wireless communica-  
tions, CATV and other wireless communication systems. The  
device operates from 2.7V and dissipates only 21 mW.  
• Operating frequency: up to 2.5 GHz with prescaler ra-  
tios of 32/33 and 64/65  
• Lock detect feature  
• Power-down mode  
• 20-pin TSSOP (Thin Shrink Small Outline Package)  
• 20-pin MLF (Micro Lead Frame)  
CYW2325 PLL Block Diagram  
V
(5)  
V (4)  
P
GND (7)  
CC  
(6)  
DO  
fp  
Prescaler  
32/33 or  
64/65  
(10)  
Phase  
Detector  
Charge  
Pump  
Binary 6-Bit  
Swallow Counter  
Binary 11-Bit  
Programmable Counter  
F
(16)  
IN  
BISW  
(15)  
FC  
(20)  
r
(18)  
18-Bit  
Latch  
p
fr  
(8)  
(1)  
(3)  
OSC_IN  
LD  
14-Bit  
Reference Counter  
OSC_OUT  
Latch  
Selector  
15-Bit  
Latch  
(14)  
(13)  
LE  
Divider  
(17)  
Output  
(fr/fp)  
MUX  
F
OUT  
DATA  
Cntrl 19-Bit  
Shift  
Reg  
(11)  
(19)  
CLOCK  
PWDN  
Pin Configuration  
OSC_IN  
NC  
1
2
20  
19  
18  
17  
16  
15  
14  
13  
12  
11  
r
PWDN  
OSC_OUT  
3
p
1
2
3
4
5
15  
14  
13  
12  
11  
Vp  
φp  
V
4
F
out  
P
Vcc  
Do  
Fout  
BISW  
FC  
V
5
BISW  
FC  
CC  
(Top View)  
D
6
GND  
LD  
O
LE  
GND  
7
LE  
LD  
8
DATA  
NC  
NC  
9
F
10  
CLOCK  
IN  
MLF  
TSSOP  
Cypress Semiconductor Corporation  
Document #: 38-07406 Rev. **  
3901 North First Street  
San Jose  
CA 95134  
408-943-2600  
Revised April 23, 2002  

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