Datasheet > CY7C1319KV18-250BZXC

CY7C1319KV18-250BZXC

更新时间： 2024-11-21 14:56:15

品牌	Logo	应用领域
英飞凌 - INFINEON		双倍数据速率
页数	文件大小	规格书
32页	816K
描述
DDR-II CIO

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CY7C1319KV18/CY7C1321KV18

18-Mbit DDR II SRAM

Four-Word Burst Architecture

18-Mbit DDR II SRAM Four-Word Burst Architecture

Features

Configurations

■ 18-Mbit density (1M × 18, 512K × 36)

■ 333-MHz clock for high bandwidth

CY7C1319KV18 – 1M × 18

CY7C1321KV18 – 512K × 36

■ Four-word burst for reducing address bus frequency

Functional Description

■ Double data rate (DDR) interfaces (data transferred at

666 MHz) at 333 MHz

CY7C1319KV18 and CY7C1321KV18 are 1.8 V Synchronous

Pipelined SRAMs equipped with DDR II architecture. The DDR

II consists of an SRAM core with advanced synchronous

peripheral circuitry and a two-bit burst counter. Addresses for

read and write are latched on alternate rising edges of the input

(K) clock. Write data is registered on the rising edges of both K

and K. Read data is driven on the rising edges of C and C if

provided, or on the rising edge of K and K if C/C are not provided.

For CY7C1319KV18 and CY7C1321KV18, the burst counter

takes in the least two significant bits of the external address and

bursts four 18-bit words in the case of CY7C1319KV18, and four

36-bit words in the case of CY7C1321KV18, sequentially into or

out of the device.

■ Two input clocks (K and K) for precise DDR timing

❐ SRAM uses rising edges only

■ Two input clocks for output data (C and C) to minimize clock

skew and flight time mismatches

■ Echo clocks (CQ and CQ) simplify data capture in high speed

systems

■ Synchronous internally self-timed writes

■ DDR II operates with 1.5 cycle read latency when DOFF is

asserted HIGH

Asynchronous inputs include an output impedance matching

input (ZQ). Synchronous data outputs (Q, sharing the same

physical pins as the data inputs, D) are tightly matched to the two

output echo clocks CQ/CQ, eliminating the need to capture data

separately from each individual DDR SRAM in the system

design. Output data clocks (C/C) enable maximum system

clocking and data synchronization flexibility.

■ Operates similar to DDR I device with one cycle read latency

when DOFF is asserted LOW

■ 1.8 V core power supply with HSTL inputs and outputs

■ Variable drive HSTL output buffers

■ Expanded HSTL output voltage (1.4 V–V_DD

)

All synchronous inputs pass through input registers controlled by

the K or K input clocks. All data outputs pass through output

registers controlled by the C or C (or K or K in a single clock

domain) input clocks. Writes are conducted with on-chip

synchronous self-timed write circuitry.

❐ Supports both 1.5 V and 1.8 V I/O supply

■ Available in 165-ball FBGA package (13 × 15 ×1.4 mm)

■ Offered in both Pb-free and non Pb-free packages

■ JTAG 1149.1 compatible test access port

For a complete list of related documentation, click here.

■ Phase locked loop (PLL) for accurate data placement

Selection Guide

Description

Maximum operating frequency

333 MHz

300

250 MHz Unit

250

320

370

MHz

Maximum operating current

× 18

× 36

370

440

Cypress Semiconductor Corporation

Document Number: 001-58906 Rev. *K

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised December 19, 2017

12 3 4 5 6 7...32

中文翻译

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与CY7C1319KV18-250BZXC相关器件

型号	品牌	获取价格	描述	数据表
CY7C1319V18	ETC	获取价格	Memory
CY7C1319V18-167BZC	CYPRESS	获取价格	DDR SRAM, 1MX18, 0.4ns, CMOS, PBGA165, 13 X 15 MM, 1.20 MM HEIGHT, FBGA-165
CY7C1319V18-300BZC	CYPRESS	获取价格	DDR SRAM, 1MX18, 0.29ns, CMOS, PBGA165, 13 X 15 MM, 1.20 MM HEIGHT, FBGA-165
CY7C131A-15JXI	CYPRESS	获取价格	1 K Ã 8 Dual-Port Static RAM
CY7C131AE	CYPRESS	获取价格	1 K / 2 K x 8 Dual-port Static RAM
CY7C131AE-15JXI	CYPRESS	获取价格	1 K / 2 K Ã 8 Dual-port Static RAM
CY7C131BV18	CYPRESS	获取价格	RAM9 QDR-I/DDR-I/QDR-II/DDR- II Errata
CY7C131CV18	CYPRESS	获取价格	RAM9 QDR-I/DDR-I/QDR-II/DDR- II Errata
CY7C131E	CYPRESS	获取价格	1 K / 2 K Ã 8 Dual-port Static RAM
CY7C131E_13	CYPRESS	获取价格	1 K / 2 K x 8 Dual-port Static RAM

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