Datasheet > CY7C1319V18

CY7C1319V18

更新时间： 2024-11-19 23:45:23

品牌	Logo	应用领域
其他 - ETC		/
页数	文件大小	规格书
23页	593K
描述
Memory

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中文翻译

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数据手册

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CY7C1319V18 数据手册

CY7C1317V18

CY7C1319V18

CY7C1321V18

PRELIMINARY

18-Mb DDR-II SRAM

Four-word Burst Architecture

Features

Functional Description

• 18-Mb density (2M x 8, 1M x 18, 512K x 36)

— Supports concurrent transactions

The CY7C1317V18/CY7C1319V18/CY7C1321V18 are 1.8V

Synchronous Pipelined SRAM equipped with DDR-II (Double

Data Rate) architecture. The DDR-II consists of an SRAM core

with advanced synchronous peripheral circuitry and a two-bit

burst counter. Addresses for Read and Write are latched on

alternate rising edges of the input (K) clock. Write data is regis-

tered on the rising edges of both K and K. Read data is driven

on the rising edges of C and C if provided, or on the rising edge

of K and K if C/C are not provided. Each address location is

associated with four 8-bit words in the case of CY7C1317V18

that burst sequentially into or out of the device. The burst

counter always starts with “00” internally in the case of

CY7C1317V18. On CY7C1319V18 and CY7C1321V18, the

burst counter takes in the last two significant bits of the

external address and bursts four 18-bit words in the case of

CY7C1319V18, and four 36-bit words in the case of

CY7C1321V18, sequentially into or out of the device.

• 250-MHz clock for high bandwidth

• Four-word burst for reducing address bus frequency

• Double Data Rate (DDR) interfaces (data transferred at

500 MHz) @ 250 MHz

• Two input clocks (K and K) for precise DDR timing

— SRAM uses rising edges only

• Two output clocks (C and C) accounts for clock skew

and flight time mismatches

• Echo clocks (CQ and CQ) simplify data capture in high

speed systems

• Synchronous internally self-timed writes

• 1.8V core power supply with HSTL inputs and outputs

• Variable drive HSTL output buffers

Asynchronous inputs include impedance match (ZQ).

Synchronous data outputs (Q, sharing the same physical pins

as the data inputs, D) are tightly matched to the two output

echo clocks CQ/CQ, eliminating the need for separately

capturing data from each individual DDR SRAM in the system

design. Output data clocks (C/C) enable maximum system

clocking and data synchronization flexibility.

• Expanded HSTL output voltage (1.4V–V_DD

• 13 x 15 mm 1.0-mm pitch fBGA package, 165-ball

(11 x 15 matrix)

• JTAG interface

• On-chip Delay Lock Loop (DLL)

)

Configurations

All synchronous inputs pass through input registers controlled

by the K or K input clocks. All data outputs pass through output

registers controlled by the C or C input clocks. Writes are

conducted with on-chip synchronous self-timed write circuitry.

CY7C1317V18 – 2M x 8

CY7C1319V18 – 1M x 18

CY7C1321V18 – 512K x 36

Logic Block Diagram (CY7C1317V18)

Burst

Logic

Write Write Write Write

Reg

(18:0)

Address

Output

Logic

Control

CLK

Gen.

R/W

Read Data Reg.

REF

Reg.

R/W

Control

Logic

BWS

[1:0]

[7:0]

Cypress Semiconductor Corporation

•

3901 North First Street

•

San Jose

•

CA 95134

•

408-943-2600

Document #: 38-05178 Rev. *A

Revised July 31, 2002

12 3 4 5 6 7...23

中文翻译

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与CY7C1319V18相关器件

型号	品牌	获取价格	描述	数据表
CY7C1319V18-167BZC	CYPRESS	获取价格	DDR SRAM, 1MX18, 0.4ns, CMOS, PBGA165, 13 X 15 MM, 1.20 MM HEIGHT, FBGA-165
CY7C1319V18-300BZC	CYPRESS	获取价格	DDR SRAM, 1MX18, 0.29ns, CMOS, PBGA165, 13 X 15 MM, 1.20 MM HEIGHT, FBGA-165
CY7C131A-15JXI	CYPRESS	获取价格	1 K Ã 8 Dual-Port Static RAM
CY7C131AE	CYPRESS	获取价格	1 K / 2 K x 8 Dual-port Static RAM
CY7C131AE-15JXI	CYPRESS	获取价格	1 K / 2 K Ã 8 Dual-port Static RAM
CY7C131BV18	CYPRESS	获取价格	RAM9 QDR-I/DDR-I/QDR-II/DDR- II Errata
CY7C131CV18	CYPRESS	获取价格	RAM9 QDR-I/DDR-I/QDR-II/DDR- II Errata
CY7C131E	CYPRESS	获取价格	1 K / 2 K Ã 8 Dual-port Static RAM
CY7C131E_13	CYPRESS	获取价格	1 K / 2 K x 8 Dual-port Static RAM
CY7C131E-15NXI	CYPRESS	获取价格	1 K / 2 K Ã 8 Dual-port Static RAM

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