Datasheet > CY7C13201KV18-333BZXC

CY7C13201KV18-333BZXC

更新时间： 2024-11-21 01:14:27

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		双倍数据速率静态存储器
页数	文件大小	规格书
23页	1138K
描述
18-Mbit DDR II SRAM 2-Word Burst Architecture

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CY7C13201KV18

18-Mbit DDR II SRAM 2-Word

Burst Architecture

Features

Functional Description

■ 18 Mbit Density (512K x 36)

The CY7C13201KV18 is 1.8V Synchronous Pipelined SRAM

equipped with DDR II architecture. The DDR II consists of an

SRAM core with advanced synchronous peripheral circuitry and

a 1-bit burst counter. Addresses for read and write are latched

on alternate rising edges of the input (K) clock. Write data is

registered on the rising edges of both K and K. Read data is

driven on the rising edges of C and C if provided, or on the rising

edge of K and K if C/C are not provided. The burst counter takes

in the least significant bit of the external address and bursts two

two 36-bit words sequentially into or out of the device.

■ 333 MHz Clock for High Bandwidth

■ 2-Word Burst to Reduce Address Bus Frequency

■ Double Data Rate (DDR) Interfaces

(data transferred at 666 MHz) at 333 MHz

■ Two Input Clocks (K and K) for Precise DDR Timing

❐ SRAM uses rising edges only

■ Two Input Clocks for Output Data (C and C) to minimize Clock

Skew and Flight Time Mismatches

Asynchronous inputs include an output impedance matching

input (ZQ). Synchronous data outputs (Q, sharing the same

physical pins as the data inputs D) are tightly matched to the two

output echo clocks CQ/CQ, eliminating the need for separately

capturing data from each individual DDR SRAM in the system

design. Output data clocks (C/C) enable maximum system

clocking and data synchronization flexibility.

■ Echo Clocks (CQ and CQ) simplify Data Capture in High Speed

Systems

■ Synchronous Internally Self Timed Writes

■ DDR II Operates with 1.5 Cycle Read Latency when DOFF is

All synchronous inputs pass through input registers controlled by

the K or K input clocks. All data outputs pass through output

registers controlled by the C or C (or K or K in a single clock

domain) input clocks. Writes are conducted with on-chip

synchronous self-timed write circuitry.

Asserted HIGH

■ Operates Similar to DDR I Device with 1 Cycle Read Latency

when DOFF is Asserted LOW

■ 1.8V Core Power Supply with HSTL Inputs and Outputs

■ Variable Drive HSTL Output Buffers

This device is down bonded from the 65 nm 72M QDRII device

and has the same I_{DD SB1}values and JTAG ID code as the

equivalent 72M device option. For details refer to the application

note AN53189, 65 nm Technology Interim QDRII/DDRII SRAM

Device Family Description.

■ Expanded HSTL Output Voltage (1.4V–V_DD

❐ Supports both 1.5V and 1.8V I/O supply

)

■ Available in 165-Ball FBGA Package (13 x 15 x 1.4 mm)

■ Offered in both Pb-free and Non Pb-free Packages

■ JTAG 1149.1 Compatible Test Access Port

■ Phase Locked Loop (PLL) for Accurate Data Placement

Configuration

CY7C13201KV18 – 512K x 36

Table 1. Selection Guide

Description

333 MHz

333

300 MHz

300

250 MHz

250

200 MHz

200

167 MHz

167

Unit

MHz

Maximum Operating Frequency

Maximum Operating Current

640

600

530

450

400

Cypress Semiconductor Corporation

Document Number: 001-54142 Rev. *B

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised September 11, 2009

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与CY7C13201KV18-333BZXC相关器件

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CY7C1320BV18-167BZI	CYPRESS	获取价格	18-Mbit DDR-II SRAM 2-Word Burst Architecture
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