Datasheet > 存储 > SRAM> CY7C1320BV18-200BZI

CY7C1320BV18-200BZI

更新时间： 2024-11-24 05:19:11

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		静态存储器双倍数据速率
页数	文件大小	规格书
28页	511K
描述
18-Mbit DDR-II SRAM 2-Word Burst Architecture

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技术参数
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CY7C1320BV18-200BZI 技术参数

是否Rohs认证：	不符合	生命周期：	Obsolete
零件包装代码：	BGA	包装说明：	13 X 15 MM, 1.40 MM HEIGHT, MO-216, FBGA-165
针数：	165	Reach Compliance Code：	not_compliant
ECCN代码：	3A991.B.2.A	HTS代码：	8542.32.00.41
风险等级：	5.3	最长访问时间：	0.45 ns
其他特性：	PIPELINED ARCHITECTURE	最大时钟频率 (fCLK)：	200 MHz
I/O 类型：	COMMON	JESD-30 代码：	R-PBGA-B165
JESD-609代码：	e0	长度：	15 mm
内存密度：	18874368 bit	内存集成电路类型：	DDR SRAM
内存宽度：	36	湿度敏感等级：	3
功能数量：	1	端子数量：	165
字数：	524288 words	字数代码：	512000
工作模式：	SYNCHRONOUS	最高工作温度：	85 °C
最低工作温度：	-40 °C	组织：	512KX36
输出特性：	3-STATE	封装主体材料：	PLASTIC/EPOXY
封装代码：	LBGA	封装等效代码：	BGA165,11X15,40
封装形状：	RECTANGULAR	封装形式：	GRID ARRAY, LOW PROFILE
并行/串行：	PARALLEL	峰值回流温度（摄氏度）：	220
电源：	1.5/1.8,1.8 V	认证状态：	Not Qualified
座面最大高度：	1.4 mm	最大待机电流：	0.22 A
最小待机电流：	1.7 V	子类别：	SRAMs
最大压摆率：	0.5 mA	最大供电电压 (Vsup)：	1.9 V
最小供电电压 (Vsup)：	1.7 V	标称供电电压 (Vsup)：	1.8 V
表面贴装：	YES	技术：	CMOS
温度等级：	INDUSTRIAL	端子面层：	Tin/Lead (Sn/Pb)
端子形式：	BALL	端子节距：	1 mm
端子位置：	BOTTOM	处于峰值回流温度下的最长时间：	NOT SPECIFIED
宽度：	13 mm

CY7C1320BV18-200BZI 数据手册

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CY7C1316BV18

CY7C1916BV18

CY7C1318BV18

CY7C1320BV18

18-Mbit DDR-II SRAM 2-Word

Burst Architecture

Features

Functional Description

• 18-Mbit density (2M x 8, 2M x 9, 1M x 18, 512K x 36)

• 300-MHz clock for high bandwidth

The CY7C1316BV18, CY7C1916BV18, CY7C1318BV18, and

CY7C1320BV18 are 1.8V Synchronous Pipelined SRAM

equipped with DDR-II architecture. The DDR-II consists of an

SRAM core with advanced synchronous peripheral circuitry

and a 1-bit burst counter. Addresses for Read and Write are

latched on alternate rising edges of the input (K) clock. Write

data is registered on the rising edges of both K and K. Read

data is driven on the rising edges of C and C if provided, or on

the rising edge of K and K if C/C are not provided. Each

address location is associated with two 8-bit words in the case

of CY7C1316BV18 and two 9-bit words in the case of

CY7C1916BV18 that burst sequentially into or out of the

device. The burst counter always starts with a “0” internally in

the case of CY7C1316BV18 and CY7C1916BV18. On

CY7C1318BV18 and CY7C1320BV18, the burst counter

takes in the least significant bit of the external address and

bursts two 18-bit words in the case of CY7C1318BV18 and two

36-bit words in the case of CY7C1320BV18 sequentially into

or out of the device.

• 2-Word burst for reducing address bus frequency

• Double Data Rate (DDR) interfaces

(data transferred at 600 MHz) @ 300 MHz

• Two input clocks (K and K) for precise DDR timing

— SRAM uses rising edges only

• Two input clocks for output data (C and C) to minimize

clock-skew and flight-time mismatches

• Echo clocks (CQ and CQ) simplify data capture in

high-speed systems

• Synchronous internally self-timed writes

• 1.8V core power supply with HSTL inputs and outputs

• Variable drive HSTL output buffers

• Expanded HSTL output voltage (1.4V–V_DD

)

Asynchronous inputs include output impedance matching

input (ZQ). Synchronous data outputs (Q, sharing the same

physical pins as the data inputs D) are tightly matched to the

two output echo clocks CQ/CQ, eliminating the need for

separately capturing data from each individual DDR SRAM in

the system design. Output data clocks (C/C) enable maximum

system clocking and data synchronization flexibility.

• Available in 165-ball FBGA package (13 x 15 x 1.4 mm)

• Offered in both lead-free and non lead-free packages

• JTAG 1149.1-compatible test access port

• Delay Lock Loop (DLL) for accurate data placement

Configurations

All synchronous inputs pass through input registers controlled

by the K or K input clocks. All data outputs pass through output

registers controlled by the C or C (or K or K in a single clock

domain) input clocks. Writes are conducted with on-chip

synchronous self-timed write circuitry.

CY7C1316BV18 – 2M x 8

CY7C1916BV18 – 2M x 9

CY7C1318BV18 – 1M x 18

CY7C1320BV18 – 512K x 36

Selection Guide

300 MHz

300

278 MHz

250 MHz

250

200 MHz

200

167 MHz

167

Unit

MHz

Maximum Operating Frequency

Maximum Operating Current

278

580

600

550

500

450

Cypress Semiconductor Corporation

Document Number: 38-05621 Rev. *C

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised June 27, 2006

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与CY7C1320BV18-200BZI相关器件

型号	品牌	获取价格	描述	数据表
CY7C1320BV18-200BZXC	CYPRESS	获取价格	18-Mbit DDR-II SRAM 2-Word Burst Architecture
CY7C1320BV18-200BZXI	CYPRESS	获取价格	18-Mbit DDR-II SRAM 2-Word Burst Architecture
CY7C1320BV18-250BZC	CYPRESS	获取价格	18-Mbit DDR-II SRAM 2-Word Burst Architecture
CY7C1320BV18-250BZI	CYPRESS	获取价格	18-Mbit DDR-II SRAM 2-Word Burst Architecture
CY7C1320BV18-250BZXC	CYPRESS	获取价格	18-Mbit DDR-II SRAM 2-Word Burst Architecture
CY7C1320BV18-250BZXI	CYPRESS	获取价格	18-Mbit DDR-II SRAM 2-Word Burst Architecture
CY7C1320BV18-278BZC	CYPRESS	获取价格	18-Mbit DDR-II SRAM 2-Word Burst Architecture
CY7C1320BV18-278BZI	CYPRESS	获取价格	18-Mbit DDR-II SRAM 2-Word Burst Architecture
CY7C1320BV18-278BZXC	CYPRESS	获取价格	18-Mbit DDR-II SRAM 2-Word Burst Architecture
CY7C1320BV18-278BZXI	CYPRESS	获取价格	18-Mbit DDR-II SRAM 2-Word Burst Architecture

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