Datasheet > CY7C1320AV18-200BZC

CY7C1320AV18-200BZC

更新时间： 2024-11-19 22:37:11

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		静态存储器双倍数据速率
页数	文件大小	规格书
20页	229K
描述
18-Mbit DDR-II SRAM 2-Word Burst Architecture

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CY7C1320AV18-200BZC 技术参数

生命周期：	Obsolete	零件包装代码：	BGA
包装说明：	LBGA, BGA165,11X15,40	针数：	165
Reach Compliance Code：	unknown	ECCN代码：	3A991.B.2.A
HTS代码：	8542.32.00.41	风险等级：	5.27
最长访问时间：	0.45 ns	其他特性：	PIPELINED ARCHITECTURE
最大时钟频率 (fCLK)：	200 MHz	I/O 类型：	COMMON
JESD-30 代码：	R-PBGA-B165	长度：	15 mm
内存密度：	18874368 bit	内存集成电路类型：	DDR SRAM
内存宽度：	36	功能数量：	1
端子数量：	165	字数：	524288 words
字数代码：	512000	工作模式：	SYNCHRONOUS
最高工作温度：	70 °C	最低工作温度：
组织：	512KX36	输出特性：	3-STATE
封装主体材料：	PLASTIC/EPOXY	封装代码：	LBGA
封装等效代码：	BGA165,11X15,40	封装形状：	RECTANGULAR
封装形式：	GRID ARRAY, LOW PROFILE	并行/串行：	PARALLEL
电源：	1.5,1.8 V	认证状态：	Not Qualified
座面最大高度：	1.4 mm	最大待机电流：	0.47 A
最小待机电流：	1.7 V	子类别：	SRAMs
最大压摆率：	0.75 mA	最大供电电压 (Vsup)：	1.9 V
最小供电电压 (Vsup)：	1.7 V	标称供电电压 (Vsup)：	1.8 V
表面贴装：	YES	技术：	CMOS
温度等级：	COMMERCIAL	端子形式：	BALL
端子节距：	1 mm	端子位置：	BOTTOM
宽度：	13 mm

CY7C1320AV18-200BZC 数据手册

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CY7C1316AV18

CY7C1318AV18

CY7C1320AV18

18-Mbit DDR-II SRAM 2-Word

Burst Architecture

Features

Functional Description

• 18-Mb density (2M x 8, 1M x 18, 512K x 36)

• 250-MHz clock for high bandwidth

The CY7C1316AV18/CY7C1318AV18/CY7C1320AV18 are

1.8V Synchronous Pipelined SRAM equipped with DDR-II

architecture. The DDR-II consists of an SRAM core with

advanced synchronous peripheral circuitry and a 1-bit burst

counter. Addresses for Read and Write are latched on

alternate rising edges of the input (K) clock. Write data is regis-

tered on the rising edges of both K and K. Read data is driven

on the rising edges of C and C if provided, or on the rising edge

of K and K if C/C are not provided. Each address location is

associated with two 8-bit words in the case of CY7C1316AV18

that burst sequentially into or out of the device. The burst

counter always starts with a “0” internally in the case of

CY7C1316AV18. On CY7C1318AV18 and CY7C1320AV18,

the burst counter takes in the least significant bit of the external

address and bursts two 18-bit words in the case of

CY7C1318AV18 and two 36-bit words in the case of

CY7C1320AV18 sequentially into or out of the device.

• 2-Word burst for reducing address bus frequency

• Double Data Rate (DDR) interfaces (data transferred at

500 MHz) @ 250 MHz

• Two input clocks (K and K) for precise DDR timing

— SRAM uses rising edges only

• Two output clocks (C and C) account for clock skew

and flight time mismatching

• Echo clocks (CQ and CQ) simplify data capture in

high-speed systems

• Synchronous internally self-timed writes

• 1.8V core power supply with HSTL inputs and outputs

• Variable drive HSTL output buffers

Asynchronous inputs include impedance match (ZQ).

Synchronous data outputs (Q, sharing the same physical pins

as the data inputs D) are tightly matched to the two output echo

clocks CQ/CQ, eliminating the need for separately capturing

data from each individual DDR SRAM in the system design.

Output data clocks (C/C) enable maximum system clocking

and data synchronization flexibility.

• Expanded HSTL output voltage (1.4V–V_DD

)

• 13 x 15 x 1.4 mm 1.0-mm pitch fBGA package, 165 ball

(11x15 matrix)

• JTAG 1149.1 compatible test access port

• Delay Lock Loop (DLL) for accurate data placement

All synchronous inputs pass through input registers controlled

by the K or K input clocks. All data outputs pass through output

registers controlled by the C or C input clocks. Writes are

conducted with on-chip synchronous self-timed write circuitry.

Configurations

CY7C1316AV18 – 2M x 8

CY7C1318AV18 – 1M x 18

CY7C1320AV18 – 512K x 36

Logic Block Diagram (CY7C1316AV18)

Write

Reg

Write

Reg

(19:0)

Address

Output

Logic

Control

CLK

Gen.

R/W

DOFF

Read Data Reg.

REF

Reg.

R/W

Control

Logic

BWS

[1:0]

[7:0]

Cypress Semiconductor Corporation

Document #: 38-05499 Rev. *B

•

3901 North First Street

•

San Jose, CA 95134

•

408-943-2600

Revised January 29, 2005

12 3 4 5 6 7...20

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与CY7C1320AV18-200BZC相关器件

型号	品牌	获取价格	描述	数据表
CY7C1320AV18-250BZC	CYPRESS	获取价格	18-Mbit DDR-II SRAM 2-Word Burst Architecture
CY7C1320BV18	CYPRESS	获取价格	18-Mbit DDR-II SRAM 2-Word Burst Architecture
CY7C1320BV18-167BZC	CYPRESS	获取价格	18-Mbit DDR-II SRAM 2-Word Burst Architecture
CY7C1320BV18-167BZI	CYPRESS	获取价格	18-Mbit DDR-II SRAM 2-Word Burst Architecture
CY7C1320BV18-167BZXC	CYPRESS	获取价格	18-Mbit DDR-II SRAM 2-Word Burst Architecture
CY7C1320BV18-167BZXI	CYPRESS	获取价格	18-Mbit DDR-II SRAM 2-Word Burst Architecture
CY7C1320BV18-200BZC	CYPRESS	获取价格	18-Mbit DDR-II SRAM 2-Word Burst Architecture
CY7C1320BV18-200BZI	CYPRESS	获取价格	18-Mbit DDR-II SRAM 2-Word Burst Architecture
CY7C1320BV18-200BZXC	CYPRESS	获取价格	18-Mbit DDR-II SRAM 2-Word Burst Architecture
CY7C1320BV18-200BZXI	CYPRESS	获取价格	18-Mbit DDR-II SRAM 2-Word Burst Architecture

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