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CY7C131AE-15JXI

更新时间： 2024-11-24 12:21:15
品牌 Logo 应用领域
赛普拉斯 - CYPRESS /
页数 文件大小 规格书
19页 347K
描述
1 K / 2 K × 8 Dual-port Static RAM

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CY7C131AE-15JXI 技术参数

是否Rohs认证： 符合生命周期：Obsolete
包装说明：QCCJ, LDCC52,.8SQReach Compliance Code：compliant
ECCN代码：3A991.B.2.BHTS代码：8542.32.00.41
风险等级：5.75最长访问时间：15 ns
I/O 类型：COMMONJESD-30 代码：S-PQCC-J52
JESD-609代码：e3长度：19.1262 mm
内存密度：8192 bit内存集成电路类型：DUAL-PORT SRAM
内存宽度：8湿度敏感等级：3
功能数量：1端口数量：2
端子数量：52字数：1024 words
字数代码：1000工作模式：ASYNCHRONOUS
最高工作温度：85 °C最低工作温度：-40 °C
组织：1KX8输出特性：3-STATE
封装主体材料：PLASTIC/EPOXY封装代码：QCCJ
封装等效代码：LDCC52,.8SQ封装形状：SQUARE
封装形式：CHIP CARRIER并行/串行：PARALLEL
峰值回流温度（摄氏度）：260电源：5 V
认证状态：Not Qualified座面最大高度：5.08 mm
最大待机电流：0.015 A最小待机电流：4.5 V
子类别：SRAMs最大压摆率：0.305 mA
最大供电电压 (Vsup)：5.5 V最小供电电压 (Vsup)：4.5 V
标称供电电压 (Vsup)：5 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子面层：Matte Tin (Sn)端子形式：J BEND
端子节距：1.27 mm端子位置：QUAD
处于峰值回流温度下的最长时间：20宽度：19.1262 mm
Base Number Matches：1

CY7C131AE-15JXI 数据手册

 浏览型号CY7C131AE-15JXI的Datasheet PDF文件第2页浏览型号CY7C131AE-15JXI的Datasheet PDF文件第3页浏览型号CY7C131AE-15JXI的Datasheet PDF文件第4页浏览型号CY7C131AE-15JXI的Datasheet PDF文件第5页浏览型号CY7C131AE-15JXI的Datasheet PDF文件第6页浏览型号CY7C131AE-15JXI的Datasheet PDF文件第7页 
CY7C131E, CY7C131AE  
CY7C136E, CY7C136AE  
1 K / 2 K × 8 Dual-port Static RAM  
1
K / 2 K × 8 Dual-port Static RAM  
Features  
Functional Description  
■ True dual-ported memory cells, which allow simultaneous  
reads of the same memory location  
CY7C131E / CY7C131AE / CY7C136E / CY7C136AE are  
high-speed, low-power CMOS 1 K / 2 K × 8 dual-port static  
RAMs. Two ports are provided permitting independent access to  
any location in memory. The CY7C131E / CY7C131AE /  
CY7C136E / CY7C136AE can be used as a standalone dual-port  
static RAM. It is the solution to applications requiring shared or  
buffered data, such as cache memory for DSP, bit-slice, or multi-  
processor designs.  
■ 1 K / 2 K × 8 organization  
■ 0.35 micron complementary metal oxide semiconductor  
(CMOS) for optimum speed and power  
■ High speed access: 15 ns  
■ Low operating power: ICC = 110 mA (typical),  
Each port has independent control pins; chip enable (CE), write  
enable (R/W), and output enable (OE). Two flags are provided  
on each port, BUSY and INT. The BUSY flag signals that the port  
is trying to access the same location, which is currently being  
accessed by the other port. The INT is an interrupt flag indicating  
that data is placed in a unique location[1]. The BUSY and INT  
flags are push pull outputs. An automatic power-down feature is  
controlled independently on each port by the chip enable (CE)  
pins.  
Standby: ISB3 = 0.05 mA (typical)  
■ Fully asynchronous operation  
■ Automatic power-down  
■ BUSY output flag to indicate access to the same location by  
both ports  
■ INT flag for port-to-port communication  
■ Available in 52-pin plastic leaded chip carrier (PLCC), 52-pin  
plastic quad flat package (PQFP)  
The CY7C131E / CY7C131AE / CY7C136E / CY7C136AE are  
available in 52-pin Pb-free PLCC and 52-pin Pb-free PQFP.  
■ Pb-free packages available  
Logic Block Diagram  
R/  
W
L
L
R/  
W
R
CE  
OE  
CE  
R
OE  
L
R
I/O  
I/O  
I/O  
I/O  
7L  
7R  
I/O  
CONTROL  
I/O  
CONTROL  
0R  
0L  
[2]  
[2]  
[4]  
BUSY  
BUSY  
R
L
A
A
A
9/10L  
0L  
9/10R  
0R  
MEMORY  
ARRAY  
ADDR  
DECODER  
ADDR  
DECODER  
[4]  
A
7C131E/7C131AE/  
7C136E/7C136AE  
ARBITRATION LOGIC  
CE  
L
CE  
R
OE  
L
OE  
R
INTERRUPT LOGIC  
R/  
W
L
R/W  
R
[3]  
L
[3]  
INT  
INT  
R
Notes  
1. Unique location used by interrupt flag: 1 K × 8: Left port reads from 3FE, Right port reads from 3FF; 2 K × 8: Left port reads from 7FE, Right port reads from 7FF.  
2. BUSY is a push-pull output. No pull-up resistor required.  
3. INT: push-pull output. No pull-up resistor required.  
4. 1 K × 8: A0–A9, 2 K × 8: A0–A10, address lines are for both left and right ports.  
Cypress Semiconductor Corporation  
Document Number: 001-64231 Rev. *D  
•
198 Champion Court  
•
San Jose, CA 95134-1709  
•
408-943-2600  
Revised June 15, 2012  
1234567...19

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