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CY7C1319V18-167BZC PDF预览

CY7C1319V18-167BZC

更新时间： 2024-11-24 21:02:47
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 双倍数据速率静态存储器内存集成电路
页数 文件大小 规格书
22页 560K
描述
DDR SRAM, 1MX18, 0.4ns, CMOS, PBGA165, 13 X 15 MM, 1.20 MM HEIGHT, FBGA-165

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CY7C1319V18-167BZC 技术参数

是否无铅： 含铅是否Rohs认证： 不符合
生命周期：Obsolete零件包装代码：BGA
包装说明：13 X 15 MM, 1.20 MM HEIGHT, FBGA-165针数：165
Reach Compliance Code：compliantECCN代码：3A991.B.2.A
HTS代码：8542.32.00.41风险等级：5.91
最长访问时间：0.4 ns其他特性：PIPELINED ARCHITECTURE
JESD-30 代码：R-PBGA-B165JESD-609代码：e0
长度：15 mm内存密度：18874368 bit
内存集成电路类型：DDR SRAM内存宽度：18
湿度敏感等级：3功能数量：1
端子数量：165字数：1048576 words
字数代码：1000000工作模式：SYNCHRONOUS
最高工作温度：70 °C最低工作温度：
组织：1MX18封装主体材料：PLASTIC/EPOXY
封装代码：TBGA封装形状：RECTANGULAR
封装形式：GRID ARRAY, THIN PROFILE并行/串行：PARALLEL
峰值回流温度（摄氏度）：220认证状态：Not Qualified
座面最大高度：1.2 mm最大供电电压 (Vsup)：1.9 V
最小供电电压 (Vsup)：1.7 V标称供电电压 (Vsup)：1.8 V
表面贴装：YES技术：CMOS
温度等级：COMMERCIAL端子面层：Tin/Lead (Sn/Pb)
端子形式：BALL端子节距：1 mm
端子位置：BOTTOM处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：13 mmBase Number Matches：1

CY7C1319V18-167BZC 数据手册

 浏览型号CY7C1319V18-167BZC的Datasheet PDF文件第2页浏览型号CY7C1319V18-167BZC的Datasheet PDF文件第3页浏览型号CY7C1319V18-167BZC的Datasheet PDF文件第4页浏览型号CY7C1319V18-167BZC的Datasheet PDF文件第5页浏览型号CY7C1319V18-167BZC的Datasheet PDF文件第6页浏览型号CY7C1319V18-167BZC的Datasheet PDF文件第7页 
CY7C1317V18  
CY7C1319V18  
CY7C1321V18  
PRELIMINARY  
18-Mb DDR™-II SRAM  
4-Word Burst Architecture  
Features  
Functional Description  
• 18-Mb density (2M x 8, 1M x 18, 512K x 36)  
• 250-MHz clock for high bandwidth  
• 4-Word burst for reducing address bus frequency  
The CY7C1317V18/CY7C1319V18/CY7C1321V18 are 1.8V  
Synchronous Pipelined SRAM equipped with DDR-II (Double  
Data Rate) architecture. The DDR-II consists of an SRAM core  
with advanced synchronous peripheral circuitry and a two-bit  
burst counter. Addresses for Read and Write are latched on  
alternate rising edges of the input (K) clock. Write data is regis-  
tered on the rising edges of both K and K. Read data is driven  
on the rising edges of C and C if provided, or on the rising edge  
of K and K if C/C are not provided. Each address location is  
associated with four 8-bit words in the case of CY7C1317V18  
that burst sequentially into or out of the device. The burst  
counter always starts with “00” internally in the case of  
CY7C1317V18. On CY7C1319V18 and CY7C1321V18, the  
burst counter takes in the last two significant bits of the  
external address and bursts four 18-bit words in the case of  
CY7C1319V18, and four 36-bit words in the case of  
CY7C1321V18, sequentially into or out of the device.  
Asynchronous inputs include impedance match (ZQ).  
Synchronous data outputs (Q, sharing the same physical pins  
as the data inputs, D) are tightly matched to the two output  
echo clocks CQ/CQ, eliminating the need for separately  
capturing data from each individual DDR-II SRAM in the  
system design. Output data clocks (C/C) enable maximum  
system clocking and data synchronization flexibility.  
• Double Data Rate (DDR™) interfaces (data transferred  
at 500 MHz) @ 250 MHz  
• Two input clocks (K and K) for precise DDR timing  
— SRAM uses rising edges only  
• Two output clocks (C and C) account for clock skew  
and flight time mismatching  
• Echo clocks (CQ and CQ) simplify data capture in  
high-speed systems  
• Synchronous internally self-timed writes  
• 1.8V core power supply with HSTL inputs and outputs  
• Variable drive HSTL output buffers  
• Expanded HSTL output voltage (1.4V–VDD  
)
• 13 x 15 mm 1.0-mm pitch fBGA package, 165-ball  
(11 x 15 matrix)  
• JTAG 1149.1 compatible test access port  
• Delay Lock Loop (DLL) for accurate data placement.  
All synchronous inputs pass through input registers controlled  
by the K or K input clocks. All data outputs pass through output  
registers controlled by the C or C input clocks. Writes are  
conducted with on-chip synchronous self-timed write circuitry.  
Configurations  
CY7C1317V18 – 2M x 8  
CY7C1319V18 – 1M x 18  
CY7C1321V18 – 512K x 36  
Logic Block Diagram (CY7C1317V18)  
Write Write Write Write  
A(18:0)  
LD  
Reg Reg Reg  
Reg  
Address  
Register  
19  
8
K
K
Output  
Logic  
CLK  
R/W  
Gen.  
Control  
C
C
DOFF  
Read Data Reg.  
32  
CQ  
CQ  
16  
VREF  
R/W  
NWS[1:0]  
Reg.  
Reg.  
Reg.  
Control  
Logic  
16  
8
DQ[7:0]  
8
Cypress Semiconductor Corporation  
•
3901 North First Street  
•
San Jose, CA 95134  
•
408-943-2600  
Document #: 38-05178 Rev. *B  
Revised February 7, 2004  
1234567...22

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