Datasheet > CY7C1319CV18-300BZXC

CY7C1319CV18-300BZXC

更新时间： 2024-11-20 03:54:35

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		静态存储器双倍数据速率
页数	文件大小	规格书
31页	700K
描述
18-Mbit DDR-II SRAM 4-Word Burst Architecture

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技术参数
数据手册

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CY7C1319CV18-300BZXC 技术参数

是否Rohs认证：	符合	生命周期：	Obsolete
零件包装代码：	BGA	包装说明：	LBGA, BGA165,11X15,40
针数：	165	Reach Compliance Code：	compliant
ECCN代码：	3A991.B.2.A	HTS代码：	8542.32.00.41
风险等级：	5.75	最长访问时间：	0.45 ns
其他特性：	PIPELINED ARCHITECTURE	最大时钟频率 (fCLK)：	300 MHz
I/O 类型：	COMMON	JESD-30 代码：	R-PBGA-B165
JESD-609代码：	e1	长度：	15 mm
内存密度：	18874368 bit	内存集成电路类型：	DDR SRAM
内存宽度：	18	湿度敏感等级：	3
功能数量：	1	端子数量：	165
字数：	1048576 words	字数代码：	1000000
工作模式：	SYNCHRONOUS	最高工作温度：	70 °C
最低工作温度：		组织：	1MX18
输出特性：	3-STATE	封装主体材料：	PLASTIC/EPOXY
封装代码：	LBGA	封装等效代码：	BGA165,11X15,40
封装形状：	RECTANGULAR	封装形式：	GRID ARRAY, LOW PROFILE
并行/串行：	PARALLEL	峰值回流温度（摄氏度）：	260
电源：	1.5/1.8,1.8 V	认证状态：	Not Qualified
座面最大高度：	1.4 mm	最大待机电流：	0.325 A
最小待机电流：	1.7 V	子类别：	SRAMs
最大压摆率：	0.81 mA	最大供电电压 (Vsup)：	1.9 V
最小供电电压 (Vsup)：	1.7 V	标称供电电压 (Vsup)：	1.8 V
表面贴装：	YES	技术：	CMOS
温度等级：	COMMERCIAL	端子面层：	Tin/Silver/Copper (Sn/Ag/Cu)
端子形式：	BALL	端子节距：	1 mm
端子位置：	BOTTOM	处于峰值回流温度下的最长时间：	30
宽度：	13 mm	Base Number Matches：	1

CY7C1319CV18-300BZXC 数据手册

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CY7C1317CV18, CY7C1917CV18

CY7C1319CV18, CY7C1321CV18

18-Mbit DDR-II SRAM 4-Word

Burst Architecture

Features

Functional Description

■ 18-Mbit density (2M x 8, 2M x 9, 1M x 18, 512K x 36)

■ 300 MHz clock for high bandwidth

The CY7C1317CV18, CY7C1917CV18, CY7C1319CV18, and

CY7C1321CV18 are 1.8V Synchronous Pipelined SRAMs

equipped with DDR-II architecture. The DDR-II consists of an

SRAM core with advanced synchronous peripheral circuitry and

a two-bit burst counter. Addresses for read and write are latched

on alternate rising edges of the input (K) clock. Write data is

registered on the rising edges of both K and K. Read data is

driven on the rising edges of C and C if provided, or on the rising

edge of K and K if C/C are not provided. Each address location

is associated with four 8-bit words in the case of CY7C1317CV18

and four 9-bit words in the case of CY7C1917CV18 that burst

sequentially into or out of the device. The burst counter always

starts with a ‘00’ internally in the case of CY7C1317CV18 and

CY7C1917CV18. For CY7C1319CV18 and CY7C1321CV18,

the burst counter takes in the least two significant bits of the

external address and bursts four 18-bit words in the case of

CY7C1319CV18, and four 36-bit words in the case of

CY7C1321CV18, sequentially into or out of the device.

■ 4-word burst for reducing address bus frequency

■ Double Data Rate (DDR) interfaces

(data transferred at 600 MHz) at 300 MHz

■ Two input clocks (K and K) for precise DDR timing

❐ SRAM uses rising edges only

■ Two input clocks for output data (C and C) to minimize clock

skew and flight time mismatches

■ Echo clocks (CQ and CQ) simplify data capture in high-speed

systems

■ Synchronous internally self-timed writes

■ DDR-II operates with 1.5 cycle read latency when the DLL is

enabled

Asynchronous inputs include an output impedance matching

input (ZQ). Synchronous data outputs (Q, sharing the same

physical pins as the data inputs, D) are tightly matched to the two

output echo clocks CQ/CQ, eliminating the need to capture data

separately from each individual DDR SRAM in the system

design. Output data clocks (C/C) enable maximum system

clocking and data synchronization flexibility.

■ Operates similar to a DDR-I device with 1 cycle read latency in

DLL off mode

■ 1.8V core power supply with HSTL inputs and outputs

■ Variable drive HSTL output buffers

■ Expanded HSTL output voltage (1.4V–V_DD

)

All synchronous inputs pass through input registers controlled by

the K or K input clocks. All data outputs pass through output

registers controlled by the C or C (or K or K in a single clock

domain) input clocks. Writes are conducted with on-chip

synchronous self-timed write circuitry.

■ Available in 165-Ball FBGA package (13 x 15 x 1.4 mm)

■ Offered in both Pb-free and non Pb-free packages

■ JTAG 1149.1 compatible test access port

■ Delay Lock Loop (DLL) for accurate data placement

Configurations

CY7C1317CV18 – 2M x 8

CY7C1917CV18 – 2M x 9

CY7C1319CV18 – 1M x 18

CY7C1321CV18 – 512K x 36

Selection Guide

Description

300 MHz

300

278 MHz

278

250 MHz

250

200 MHz

200

167 MHz

167

Unit

MHz

Maximum Operating Frequency

Maximum Operating Current

770

720

670

580

515

770

720

670

580

515

x18

x36

810

760

700

600

540

890

830

765

655

600

Cypress Semiconductor Corporation

Document Number: 001-07161 Rev. *B

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised September 26, 2007

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与CY7C1319CV18-300BZXC相关器件

型号	品牌	获取价格	描述	数据表
CY7C1319CV18-300BZXI	CYPRESS	获取价格	18-Mbit DDR-II SRAM 4-Word Burst Architecture
CY7C1319KV18	CYPRESS	获取价格	18-Mbit DDR II SRAM Four-Word Burst Architecture
CY7C1319KV18_12	CYPRESS	获取价格	18-Mbit DDR II SRAM Four-Word Burst Architecture
CY7C1319KV18_13	CYPRESS	获取价格	18-Mbit DDR II SRAM Four-Word Burst Architecture
CY7C1319KV18-250BZC	CYPRESS	获取价格	18-Mbit DDR II SRAM Four-Word Burst Architecture 333-MHz clock for high bandwidth
CY7C1319KV18-250BZXC	CYPRESS	获取价格	18-Mbit DDR II SRAM Four-Word Burst Architecture
CY7C1319KV18-250BZXC	INFINEON	获取价格	DDR-II CIO
CY7C1319V18	ETC	获取价格	Memory
CY7C1319V18-167BZC	CYPRESS	获取价格	DDR SRAM, 1MX18, 0.4ns, CMOS, PBGA165, 13 X 15 MM, 1.20 MM HEIGHT, FBGA-165
CY7C1319V18-300BZC	CYPRESS	获取价格	DDR SRAM, 1MX18, 0.29ns, CMOS, PBGA165, 13 X 15 MM, 1.20 MM HEIGHT, FBGA-165

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