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CY7C1319KV18-250BZC PDF预览

CY7C1319KV18-250BZC

更新时间： 2024-11-24 09:43:47
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 存储内存集成电路静态存储器双倍数据速率时钟
页数 文件大小 规格书
33页 756K
描述
18-Mbit DDR II SRAM Four-Word Burst Architecture 333-MHz clock for high bandwidth

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CY7C1319KV18-250BZC 技术参数

是否Rohs认证： 不符合生命周期：End Of Life
零件包装代码：BGA包装说明：FBGA-165
针数：165Reach Compliance Code：compliant
ECCN代码：3A991.B.2.AHTS代码：8542.32.00.41
风险等级：5.53Is Samacsys：N
最长访问时间：450 ns其他特性：PIPELINED ARCHITECTURE
最大时钟频率 (fCLK)：250 MHzI/O 类型：COMMON
JESD-30 代码：R-PBGA-B165JESD-609代码：e0
长度：15 mm内存密度：18874368 bit
内存集成电路类型：DDR SRAM内存宽度：18
功能数量：1端子数量：165
字数：1048576 words字数代码：1000000
工作模式：SYNCHRONOUS最高工作温度：70 °C
最低工作温度：组织：1MX18
输出特性：3-STATE封装主体材料：PLASTIC/EPOXY
封装代码：LBGA封装等效代码：BGA165,11X15,40
封装形状：RECTANGULAR封装形式：GRID ARRAY, LOW PROFILE
并行/串行：SERIAL峰值回流温度（摄氏度）：240
电源：1.5/1.8,1.8 V认证状态：Not Qualified
座面最大高度：1.4 mm最大待机电流：0.25 A
最小待机电流：1.7 V子类别：SRAMs
最大压摆率：0.32 mA最大供电电压 (Vsup)：1.9 V
最小供电电压 (Vsup)：1.7 V标称供电电压 (Vsup)：1.8 V
表面贴装：YES技术：CMOS
温度等级：COMMERCIAL端子面层：Tin/Lead (Sn/Pb)
端子形式：BALL端子节距：1 mm
端子位置：BOTTOM处于峰值回流温度下的最长时间：30
宽度：13 mmBase Number Matches：1

CY7C1319KV18-250BZC 数据手册

 浏览型号CY7C1319KV18-250BZC的Datasheet PDF文件第2页浏览型号CY7C1319KV18-250BZC的Datasheet PDF文件第3页浏览型号CY7C1319KV18-250BZC的Datasheet PDF文件第4页浏览型号CY7C1319KV18-250BZC的Datasheet PDF文件第5页浏览型号CY7C1319KV18-250BZC的Datasheet PDF文件第6页浏览型号CY7C1319KV18-250BZC的Datasheet PDF文件第7页 
CY7C1317KV18, CY7C1917KV18  
CY7C1319KV18, CY7C1321KV18  
18-Mbit DDR II SRAM  
Four-Word Burst Architecture  
18-Mbit DDR II SRAM Four-Word Burst Architecture  
Features  
Configurations  
■ 18-Mbit density (2 M × 8, 2 M × 9, 1 M × 18, 512 K × 36)  
■ 333-MHz clock for high bandwidth  
CY7C1317KV18 – 2 M × 8  
CY7C1917KV18 – 2 M × 9  
CY7C1319KV18 – 1 M × 18  
CY7C1321KV18 – 512 K × 36  
■ Four-word burst for reducing address bus frequency  
■ Double data rate (DDR) interfaces  
(data transferred at 666 MHz) at 333 MHz  
Functional Description  
■ Two input clocks (K and K) for precise DDR timing  
❐ SRAM uses rising edges only  
The CY7C1317KV18, CY7C1917KV18, CY7C1319KV18, and  
CY7C1321KV18 are 1.8 V Synchronous Pipelined SRAMs  
equipped with DDR II architecture. The DDR II consists of an  
SRAM core with advanced synchronous peripheral circuitry and  
a two-bit burst counter. Addresses for read and write are latched  
on alternate rising edges of the input (K) clock. Write data is  
registered on the rising edges of both K and K. Read data is  
driven on the rising edges of C and C if provided, or on the rising  
edge of K and K if C/C are not provided. Each address location  
is associated with four 8-bit words in the case of CY7C1317KV18  
and four 9-bit words in the case of CY7C1917KV18 that burst  
sequentially into or out of the device. The burst counter always  
starts with a ‘00’ internally in the case of CY7C1317KV18 and  
CY7C1917KV18. For CY7C1319KV18 and CY7C1321KV18,  
the burst counter takes in the least two significant bits of the  
external address and bursts four 18-bit words in the case of  
CY7C1319KV18, and four 36-bit words in the case of  
CY7C1321KV18, sequentially into or out of the device.  
■ Two input clocks for output data (C and C) to minimize clock  
skew and flight time mismatches  
■ Echo clocks (CQ and CQ) simplify data capture in high speed  
systems  
■ Synchronous internally self-timed writes  
■ DDR II operates with 1.5 cycle read latency when DOFF is  
asserted HIGH  
■ Operates similar to DDR I device with one cycle read latency  
when DOFF is asserted LOW  
■ 1.8 V core power supply with HSTL inputs and outputs  
■ Variable drive HSTL output buffers  
■ Expanded HSTL output voltage (1.4 V–VDD  
)
❐ Supports both 1.5 V and 1.8 V I/O supply  
Asynchronous inputs include an output impedance matching  
input (ZQ). Synchronous data outputs (Q, sharing the same  
physical pins as the data inputs, D) are tightly matched to the two  
output echo clocks CQ/CQ, eliminating the need to capture data  
separately from each individual DDR SRAM in the system  
design. Output data clocks (C/C) enable maximum system  
clocking and data synchronization flexibility.  
■ Available in 165-ball FBGA package (13 × 15 ×1.4 mm)  
■ Offered in both Pb-free and non Pb-free packages  
■ JTAG 1149.1 compatible test access port  
■ Phase locked loop (PLL) for accurate data placement  
All synchronous inputs pass through input registers controlled by  
the K or K input clocks. All data outputs pass through output  
registers controlled by the C or C (or K or K in a single clock  
domain) input clocks. Writes are conducted with on-chip  
synchronous self-timed write circuitry.  
Selection Guide  
Description  
Maximum operating frequency  
Maximum operating current  
333 MHz  
300  
300 MHz  
300  
250 MHz  
250  
200 MHz  
200  
167 MHz  
167  
Unit  
MHz  
mA  
× 8  
× 9  
370  
350  
320  
280  
260  
370  
350  
320  
280  
260  
× 18  
× 36  
370  
350  
320  
290  
270  
440  
420  
370  
330  
300  
Cypress Semiconductor Corporation  
Document Number: 001-58906 Rev. *D  
•
198 Champion Court  
•
San Jose, CA 95134-1709  
•
408-943-2600  
Revised July 20, 2011  
[+] Feedback  
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CY7C1319KV18-250BZC 替代型号

型号 品牌 替代类型 描述 数据表
CY7C1319KV18-250BZXC CYPRESS

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