CY7C1214H-100AXC

更新时间： 2024-09-17 02:53:35

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		静态存储器
页数	文件大小	规格书
15页	355K
描述
1-Mbit (32K x 32) Flow-Through Sync SRAM

阅读下载

中文翻译

获取价格

数据手册

如果您发现信息不准确，欢迎纠错

CY7C1214H-100AXC 数据手册

CY7C1214H

1-Mbit (32K x 32) Flow-Through Sync SRAM

Features

Functional Description^[1]

The CY7C1214H is a 32K x 32 synchronous cache RAM

designed to interface with high-speed microprocessors with

minimum glue logic. Maximum access delay from clock rise is

6.5 ns (133-MHz version). A 2-bit on-chip counter captures the

first address in a burst and increments the address automati-

cally for the rest of the burst access. All synchronous inputs

are gated by registers controlled by a positive-edge-triggered

Clock Input (CLK). The synchronous inputs include all

addresses, all data inputs, address-pipelining Chip Enable

(CE₁), depth-expansion Chip Enables (CE₂and CE₃), Burst

Control inputs (ADSC, ADSP, and ADV), Write Enables

(BW_[A:D], and BWE), and Global Write (GW). Asynchronous

inputs include the Output Enable (OE) and the ZZ pin.

• 32K X 32 common I/O

• 3.3V core power supply (V_DD

)

• 2.5V/3.3V I/O power supply (V_DDQ

)

• Fast clock-to-output times

— 6.5 ns (for 133-MHz version)

• Provide high-performance 2-1-1-1 access rate

• User-selectable burst counter supporting Intel^®

Pentium^®interleaved or linear burst sequences

• Separate processor and controller address strobes

• Synchronous self-timed write

The CY7C1214H allows either interleaved or linear burst

sequences, selected by the MODE input pin. A HIGH selects

an interleaved burst sequence, while a LOW selects a linear

burst sequence. Burst accesses can be initiated with the

Processor Address Strobe (ADSP) or the cache Controller

Address Strobe (ADSC) inputs. Address advancement is

controlled by the Address Advancement (ADV) input.

• Asynchronous output enable

• Available in JEDEC-standard lead-free 100-Pin TQFP

package

• “ZZ” Sleep Mode option

Addresses and chip enables are registered at rising edge of

clock when either Address Strobe Processor (ADSP) or

Address Strobe Controller (ADSC) are active. Subsequent

burst addresses can be internally generated as controlled by

the Advance pin (ADV).

The CY7C1214H operates from a +3.3V core power supply

while all outputs may operate either with a +2.5V or +3.3V

supply. All inputs and outputs are JEDEC-standard

JESD8-5-compatible.

Logic Block Diagram

ADDRESS

A0, A1, A

A[1:0]

MODE

ADV

CLK

BURST

COUNTER

AND LOGIC

CLR

ADSC

ADSP

BYTE

WRITE REGISTER

BYTE

WRITE REGISTER

BYTE

WRITE REGISTER

OUTPUT

BUFFERS

WRITE REGISTER

MEMORY

ARRAY

SENSE

AMPS

DQs

BYTE

WRITE REGISTER

BYTE

WRITE REGISTER

BYTE

BWE

WRITE REGISTER

INPUT

REGISTERS

ENABLE

CE1

CE2

CE3

SLEEP

CONTROL

Note:

1. For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.

Cypress Semiconductor Corporation

Document #: 38-05671 Rev. *B

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised July 6, 2006

12 3 4 5 6 7...15

中文翻译

下载PDF

与CY7C1214H-100AXC相关器件

型号	品牌	获取价格	描述	数据表
CY7C1214H-100AXI	CYPRESS	获取价格	1-Mbit (32K x 32) Flow-Through Sync SRAM
CY7C1214H-133AXC	CYPRESS	获取价格	1-Mbit (32K x 32) Flow-Through Sync SRAM
CY7C1214H-133AXI	CYPRESS	获取价格	1-Mbit (32K x 32) Flow-Through Sync SRAM
CY7C1215F	CYPRESS	获取价格	1-Mb (32K x 32) Pipelined Sync SRAM
CY7C1215F-133AC	CYPRESS	获取价格	1-Mb (32K x 32) Pipelined Sync SRAM
CY7C1215F-133ACT	CYPRESS	获取价格	Cache SRAM, 32KX32, 4ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100
CY7C1215F-133AXC	CYPRESS	获取价格	Cache SRAM, 32KX32, 4ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100
CY7C1215F-166AC	CYPRESS	获取价格	1-Mb (32K x 32) Pipelined Sync SRAM
CY7C1215F-166ACT	CYPRESS	获取价格	暂无描述
CY7C1215H	CYPRESS	获取价格	1-Mbit (32K x 32) Pipelined Sync SRAM

与CY7C1214H-100AXC相关文章

摩尔斯微电子在美国约书亚树国家公园测试 Wi-Fi HaLow
2024-09-18

18
贸泽上架Tallysman TW5386智能GNSS天线
2024-09-18

16
SL74HC10N：高性能三输入与非门解析
2024-09-03

93
AIC1781A 电池充电控制器深度解析
2024-09-03

83

产品中心

服务支持

精选活动

关于我们

帮助中心

CY7C1214H-100AXC

CY7C1214H-100AXC 数据手册

与CY7C1214H-100AXC相关器件

与CY7C1214H-100AXC相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

CY7C1214H-100AXC

CY7C1214H-100AXC 数据手册

与CY7C1214H-100AXC相关器件

与CY7C1214H-100AXC相关文章

您还可以找

您在本页遇到什么问题？