CY7C1214F-100AC

更新时间： 2024-09-17 04:35:07

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		静态存储器
页数	文件大小	规格书
15页	286K
描述
1-Mb (32K x 32) Flow-Through Sync SRAM

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数据手册

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CY7C1214F-100AC 数据手册

CY7C1214F

1-Mb (32K x 32) Flow-Through Sync SRAM

7.5 ns (117-MHz version). A 2-bit on-chip counter captures the

first address in a burst and increments the address automati-

cally for the rest of the burst access. All synchronous inputs

are gated by registers controlled by a positive-edge-triggered

Features

• 32K X 32 common I/O

• 3.3V –5% and +10% core power supply (V_DD

)

Clock Input (CLK). The synchronous inputs include all

addresses, all data inputs, address-pipelining Chip Enable

• 3.3V I/O supply (V_DDQ

)

(

), depth-expansion Chip Enables (CE and

), Burst

CE₃

• Fast clock-to-output times

— 7.5 ns (117-MHz version)

— 8.5 ns (100-MHz version)

CE₁

Control inputs (

), Write Enables

). Asynchronous

and

ADV

ADSC ADSP

(

and

), and Global Write (

BW_[A:D]

BWE

(

)

and the ZZ pin

nputs include the Output Enable

• Provide high-performance 2-1-1-1 access rate

The CY7C1214F allows either interleaved or linear burst

sequences, selected by the MODE input pin. A HIGH selects

an interleaved burst sequence, while a LOW selects a linear

burst sequence. Burst accesses can be initiated with the

Processor Address Strobe (ADSP) or the cache Controller

Address Strobe (ADSC) inputs. Address advancement is

controlled by the Address Advancement (ADV) input.

• User-selectable burst counter supporting Intel^

Pentium^interleaved or linear burst sequences

• Separate processor and controller address strobes

• Synchronous self-timed write

• Asynchronous output enable

• Supports 3.3V I/O level

Addresses and chip enables are registered at rising edge of

clock when either Address Strobe Processor (

) or

ADSP

• Offered in JEDEC-standard 100-pin TQFP package

• “ZZ” Sleep Mode option

Address Strobe Controller (

) are active. Subsequent

ADSC

burst addresses can be internally generated as controlled by

the Advance pin ( ).

ADV

Functional Description^[1]

The CY7C1214F operates from a +3.3V core power supply

while all outputs may operate with a +3.3V supply. All inputs

and outputs are JEDEC-standard JESD8-5-compatible.

The CY7C1214F is a 32,768 x 32 synchronous cache RAM

designed to interface with high-speed microprocessors with

minimum glue logic. Maximum access delay from clock rise is

Logic Block Diagram

ADDRESS

A0, A1, A

A[1:0]

MODE

ADV

CLK

BURST

COUNTER

AND LOGIC

CLR

ADSC

ADSP

BYTE

WRITE REGISTER

BYTE

WRITE REGISTER

BYTE

WRITE REGISTER

OUTPUT

BUFFERS

WRITE REGISTER

MEMORY

ARRAY

SENSE

AMPS

DQs

BYTE

WRITE REGISTER

BYTE

WRITE REGISTER

BYTE

BWE

WRITE REGISTER

INPUT

REGISTERS

ENABLE

CE1

CE2

CE3

SLEEP

CONTROL

Note:

1. For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com

Cypress Semiconductor Corporation

•

3901 North First Street

•

San Jose, CA 95134

•

408-943-2600

Document #: 38-05434 Rev. *A

Revised March 24, 2004

12 3 4 5 6 7...15

中文翻译

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与CY7C1214F-100AC相关器件

型号	品牌	获取价格	描述	数据表
CY7C1214F-100ACT	CYPRESS	获取价格	Cache SRAM, 32KX32, 8.5ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100
CY7C1214F-117AC	CYPRESS	获取价格	Standard SRAM, 32KX32, 7.5ns, CMOS, PQFP100
CY7C1214H	CYPRESS	获取价格	1-Mbit (32K x 32) Flow-Through Sync SRAM
CY7C1214H-100AXC	CYPRESS	获取价格	1-Mbit (32K x 32) Flow-Through Sync SRAM
CY7C1214H-100AXI	CYPRESS	获取价格	1-Mbit (32K x 32) Flow-Through Sync SRAM
CY7C1214H-133AXC	CYPRESS	获取价格	1-Mbit (32K x 32) Flow-Through Sync SRAM
CY7C1214H-133AXI	CYPRESS	获取价格	1-Mbit (32K x 32) Flow-Through Sync SRAM
CY7C1215F	CYPRESS	获取价格	1-Mb (32K x 32) Pipelined Sync SRAM
CY7C1215F-133AC	CYPRESS	获取价格	1-Mb (32K x 32) Pipelined Sync SRAM
CY7C1215F-133ACT	CYPRESS	获取价格	Cache SRAM, 32KX32, 4ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100

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