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CY7C1049D-10VXI PDF预览

CY7C1049D-10VXI

更新时间: 2024-09-17 03:01:11
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 存储内存集成电路静态存储器光电二极管
页数 文件大小 规格书
8页 391K
描述
4-Mbit (512K x 8) Static RAM

CY7C1049D-10VXI 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:SOJ
包装说明:SOJ, SOJ36,.44针数:36
Reach Compliance Code:compliantECCN代码:3A991.B.2.B
HTS代码:8542.32.00.41风险等级:7.81
Is Samacsys:N最长访问时间:10 ns
I/O 类型:COMMONJESD-30 代码:R-PDSO-J36
JESD-609代码:e4长度:23.495 mm
内存密度:4194304 bit内存集成电路类型:STANDARD SRAM
内存宽度:8湿度敏感等级:3
功能数量:1端子数量:36
字数:524288 words字数代码:512000
工作模式:ASYNCHRONOUS最高工作温度:85 °C
最低工作温度:-40 °C组织:512KX8
输出特性:3-STATE封装主体材料:PLASTIC/EPOXY
封装代码:SOJ封装等效代码:SOJ36,.44
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
并行/串行:PARALLEL峰值回流温度(摄氏度):245
电源:5 V认证状态:Not Qualified
座面最大高度:3.7592 mm最大待机电流:0.01 A
最小待机电流:2 V子类别:SRAMs
最大压摆率:0.09 mA最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式:J BEND端子节距:1.27 mm
端子位置:DUAL处于峰值回流温度下的最长时间:40
宽度:10.16 mmBase Number Matches:1

CY7C1049D-10VXI 数据手册

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CY7C1049D  
4-Mbit (512K x 8) Static RAM  
Features  
Functional Description[1]  
• Pin- and function-compatible with CY7C1049B  
• High speed  
The CY7C1049D is a high-performance CMOS static RAM  
organized as 512K words by 8 bits. Easy memory expansion  
is provided by an active LOW Chip Enable (CE), an active  
LOW Output Enable (OE), and tri-state drivers. Writing to the  
device is accomplished by taking Chip Enable (CE) and Write  
Enable (WE) inputs LOW. Data on the eight I/O pins (I/O0  
through I/O7) is then written into the location specified on the  
address pins (A0 through A18).  
— tAA = 10 ns  
• Low active power  
— ICC = 90 mA @ 10 ns  
• Low CMOS Standby power  
— ISB2 = 10 mA  
Reading from the device is accomplished by taking Chip  
Enable (CE) and Output Enable (OE) LOW while forcing Write  
Enable (WE) HIGH. Under these conditions, the contents of  
the memory location specified by the address pins will appear  
on the I/O pins.  
• 2.0V Data Retention  
• Automatic power-down when deselected  
• TTL-compatible inputs and outputs  
• Easy memory expansion with CE and OE features  
The eight input/output pins (I/O0 through I/O7) are placed in a  
high-impedance state when the device is deselected (CE  
HIGH), the outputs are disabled (OE HIGH), or during a write  
operation (CE LOW, and WE LOW).  
• Available in lead-free 36-Lead (400-Mil) Molded SOJ  
package  
The CY7C1049D is available in a standard 400-mil-wide  
36-pin SOJ package with center power and ground (revolu-  
tionary) pinout.  
Logic Block Diagram  
Pin Configuration  
SOJ  
Top View  
A
A
36  
35  
34  
33  
1
NC  
0
1
2
3
4
A
A
A
A
18  
17  
16  
15  
A
2
A
A
3
4
32  
31  
30  
29  
28  
27  
26  
25  
5
I/O  
CE  
I/O  
0
6
OE  
I/O  
INPUT BUFFER  
7
8
9
10  
11  
12  
13  
0
1
7
I/O  
I/O  
V
A
0
6
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
1
A
GND  
CC  
1
GND  
I/O  
I/O3  
WE  
A
V
2
CC  
2
I/O  
I/O  
A
A
A
A
2
5
4
3
A
4
24  
23  
22  
21  
20  
19  
A
14  
13  
12  
5
3
4
5
512K x 8  
A
5
A
A
7
A
A
14  
15  
16  
17  
18  
6
A
6
7
A
A
A
11  
10  
8
9
A
8
A
9
NC  
A
10  
6
7
POWER  
DOWN  
COLUMN  
DECODER  
CE  
I/O  
WE  
OE  
Selection Guide  
-10  
10  
90  
10  
Unit  
ns  
Maximum Access Time  
Maximum Operating Current  
mA  
mA  
Maximum CMOS Standby Current  
Note:  
1. For guidelines on SRAM system design, please refer to the ‘System Design Guidelines’ Cypress application note, available on the internet at www.cypress.com.  
Cypress Semiconductor Corporation  
Document #: 38-05474 Rev. *C  
198 Champion Court  
San Jose, CA 95134-1709  
408-943-2600  
Revised April 3, 2006  
[+] Feedback  

CY7C1049D-10VXI 替代型号

型号 品牌 替代类型 描述 数据表
CY7C1049G-10VXI CYPRESS

完全替代

4-Mbit (512K words × 8 bit) Static RAM with
IS61LV5128AL-10KLI ISSI

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512K x 8 HIGH-SPEED CMOS STATIC RAM

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