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CY7C1049DV33-10VXI

更新时间： 2024-09-17 03:14:23
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赛普拉斯 - CYPRESS /
页数 文件大小 规格书
8页 432K
描述
4-Mbit (512K x 8) Static RAM

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CY7C1049DV33-10VXI 数据手册

 浏览型号CY7C1049DV33-10VXI的Datasheet PDF文件第2页浏览型号CY7C1049DV33-10VXI的Datasheet PDF文件第3页浏览型号CY7C1049DV33-10VXI的Datasheet PDF文件第4页浏览型号CY7C1049DV33-10VXI的Datasheet PDF文件第5页浏览型号CY7C1049DV33-10VXI的Datasheet PDF文件第6页浏览型号CY7C1049DV33-10VXI的Datasheet PDF文件第7页 
CY7C1049DV33  
4-Mbit (512K x 8) Static RAM  
Features  
Functional Description[1]  
• Pin- and function-compatible with CY7C1049CV33  
• High speed  
The CY7C1049DV33 is a high-performance CMOS Static  
RAM organized as 512K words by 8 bits. Easy memory  
expansion is provided by an active LOW Chip Enable (CE), an  
active LOW Output Enable (OE), and tri-state drivers. Writing  
to the device is accomplished by taking Chip Enable (CE) and  
Write Enable (WE) inputs LOW. Data on the eight I/O pins (I/O0  
through I/O7) is then written into the location specified on the  
address pins (A0 through A18).  
— tAA = 10 ns  
• Low active power  
— ICC = 90 mA @ 10 ns (Industrial)  
• Low CMOS standby power  
— ISB2 = 10 mA  
Reading from the device is accomplished by taking Chip  
Enable (CE) and Output Enable (OE) LOW while forcing Write  
Enable (WE) HIGH. Under these conditions, the contents of  
the memory location specified by the address pins will appear  
on the I/O pins.  
• 2.0V data retention  
• Automatic power-down when deselected  
• TTL-compatible inputs and outputs  
• Easy memory expansion with CE and OE features  
The eight input/output pins (I/O0 through I/O7) are placed in a  
high-impedance state when the device is deselected (CE  
HIGH), the outputs are disabled (OE HIGH), or during a Write  
operation (CE LOW, and WE LOW).  
• Available in Lead-Free 36-lead (400-mil) Molded SOJ  
V36 and 44-pin TSOP II ZS44 packages  
The CY7C1049DV33 is available in standard 400-mil-wide  
36-pin SOJ package and 44-pin TSOP II package with center  
power and ground (revolutionary) pinout.  
Pin Configuration  
Logic Block Diagram  
TSOP II  
SOJ  
Top View  
Top View  
44  
1
NC  
NC  
NC  
NC  
NC  
A18  
A17  
A16  
A15  
OE  
I/O  
A0  
A1  
36  
1
NC  
A18  
A17  
A16  
A15  
43  
42  
41  
40  
39  
38  
2
3
4
5
6
35  
34  
33  
2
3
4
A
0
A2  
A
1
A3  
A4  
A
2
32  
5
A3  
A4  
I/O  
0
7
CE  
I/O0  
I/O1  
VCC  
INPUTBUFFER  
31  
30  
29  
28  
6
OE  
I/O7  
I/O6  
37  
36  
35  
34  
33  
CE  
I/O  
8
A
0
I/O  
I/O  
7
8
9
10  
11  
12  
13  
1
A
1
9
0
7
A
2
10  
11  
12  
13  
I/O  
V
SS  
I/O  
SS  
1
CC  
6
2
A
3
4
GND  
V
A
27  
26  
25  
GND  
I/O2  
I/O3  
WE  
VCC  
I/O5  
I/O4  
A14  
A13  
A12  
V
A
6
V
5
I/O  
3
I/O  
4
I/O  
5
CC  
512K x 8  
A
32  
I/O  
I/O  
I/O  
2
5
4
A
7
31  
30  
29  
28  
I/O  
14  
15  
16  
17  
18  
19  
20  
21  
22  
3
A
8
A
WE  
A5  
A6  
A14  
A13  
24  
23  
22  
21  
20  
19  
9
A
10  
A5  
A6  
A7  
A8  
A9  
14  
15  
16  
17  
18  
A12  
27  
26  
25  
A
11  
A
I/O  
7
6
7
POWER  
DOWN  
COLUMN  
DECODER  
A11  
A10  
NC  
A
8
A
10  
CE  
A
NC  
NC  
NC  
9
I/O  
WE  
NC  
NC  
24  
23  
OE  
Selection Guide  
-10 (Industrial)  
-12 (Automotive)[2]  
Unit  
ns  
Maximum Access Time  
10  
90  
10  
12  
95  
15  
Maximum Operating Current  
mA  
mA  
Maximum CMOS Standby Current  
Notes:  
1. For guidelines on SRAM system design, please refer to the ‘System Design Guidelines’ Cypress application note, available on the internet at www.cypress.com.  
2. Automotive product information is Preliminary.  
Cypress Semiconductor Corporation  
Document #: 38-05475 Rev. *C  
•
198 Champion Court  
•
San Jose, CA 95134-1709  
•
408-943-2600  
Revised April 3, 2006  
[+] Feedback  
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CY7C1049DV33-10VXI 替代型号

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CY7C1049DV33-12VXI CYPRESS

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