Datasheet > CY7C1049G18-15ZSXIT

CY7C1049G18-15ZSXIT

更新时间： 2024-11-10 00:51:43

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		/
页数	文件大小	规格书
19页	526K
描述
4-Mbit (512K words Ã 8 bit) Static RAM with Error-Correcting Code (ECC)

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CY7C1049G

CY7C1049GE

4-Mbit (512K words × 8 bit) Static RAM

with Error-Correcting Code (ECC)

4-Mbit (512K words

× 8 bit) Static RAM with Error-Correcting Code (ECC)

offered in single and dual chip-enable options and in multiple pin

configurations. The CY7C1049GE device includes an ERR pin

that signals an error-detection and correction event during a read

cycle.

Features

■ High speed

❐ t_AA= 10 ns

■ Embedded ECC for single-bit error correction^[1]

Data writes are performed by asserting the Chip Enable (CE) and

Write Enable (WE) inputs LOW, while providing the data on I/O₀

through I/O₇and address on A₀through A₁₈pins.

■ Low active and standby currents

❐ Active current: I_CC= 38 mA typical

❐ Standby current: I_SB2= 6 mA typical

Data reads are performed by asserting the Chip Enable (CE) and

Output Enable (OE) inputs LOW and providing the required

address on the address lines. Read data is accessible on the I/O

lines (I/O₀through I/O₇).

■ Operating voltage range: 1.65 V to 2.2 V, 2.2 V to 3.6 V, and

4.5 V to 5.5 V

■ 1.0-V data retention

All I/Os (I/O₀through I/O₇) are placed in a high-impedance state

during the following events:

■ TTL-compatible inputs and outputs

■ The device is deselected (CE HIGH)

■ The control signal OE is de-asserted

■ Error indication (ERR) pin to indicate 1-bit error detection and

correction

■ Pb-free 36-pin SOJ and 44-pin TSOP II packages

On the CY7C1049GE devices, the detection and correction of a

single-bit error in the accessed location is indicated by the

assertion of the ERR output (ERR = HIGH)^[1]. See the Truth

Table on page 14 for a complete description of read and write

modes.

Functional Description

CY7C1049G and CY7C1049GE are high-performance CMOS

fast static RAM devices with embedded ECC. Both devices are

The logic block diagram is on page 2.

Product Portfolio

Power Dissipation

Speed

(ns)

Operating I_CC

Features and Options (see Pin

Configurations on page 4)

V_CCRange

(V)

Standby, I_SB2

Product^[2]

Range

(mA)

f = f_max

10/15

Typ^[3]

Max

Typ^[3]

Max

CY7C1049G(E)18 Single or Dual Chip Enables

Industrial 1.65 V–2.2 V

2.2 V–3.6 V

–

CY7C1049G(E)30

Optional ERR pins

CY7C1049G(E)

4.5 V–5.5 V

Notes

1. This device does not support automatic write-back on error detection.

2. The ERR pin is available only for devices which have ERR option “E” in the ordering code. Refer Ordering Information on page 15 for details.

3. Typical values are included only for reference and are not guaranteed or tested. Typical values are measured at V = 1.8 V (for a V range of 1.65 V–2.2 V),

= 3 V (for a V range of 2.2 V–3.6 V), and V = 5 V (for a V range of 4.5 V–5.5 V), T = 25 °C.

CC CC CC A

Cypress Semiconductor Corporation

Document Number: 001-95412 Rev. *E

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised May 3, 2017

12 3 4 5 6 7...19

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CY7C1049G30-10VXI	CYPRESS	获取价格	4-Mbit (512K words Ã 8 bit) Static RAM with
CY7C1049G30-10VXI	INFINEON	获取价格	Asynchronous SRAM
CY7C1049G30-10VXIT	CYPRESS	获取价格	4-Mbit (512K words Ã 8 bit) Static RAM with
CY7C1049G30-10VXIT	INFINEON	获取价格	Asynchronous SRAM
CY7C1049G30-10ZSXI	CYPRESS	获取价格	4-Mbit (512K words Ã 8 bit) Static RAM with
CY7C1049G30-10ZSXI	INFINEON	获取价格	Asynchronous SRAM
CY7C1049G30-10ZSXIT	CYPRESS	获取价格	4-Mbit (512K words Ã 8 bit) Static RAM with
CY7C1049GE30-10ZSXI	CYPRESS	获取价格	Standard SRAM, 512KX8, 10ns, CMOS, PDSO44, TSOP2-44
CY7C1049GE30-10ZSXI	INFINEON	获取价格	Asynchronous SRAM
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