Datasheet > CY7C1019D_10

CY7C1019D_10

更新时间： 2024-11-14 09:43:27

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		/
页数	文件大小	规格书
13页	887K
描述
1-Mbit (128K x 8) Static RAM

阅读下载

中文翻译

获取价格

数据手册

如果您发现信息不准确，欢迎纠错

CY7C1019D_10 数据手册

CY7C1019D

1-Mbit (128K x 8) Static RAM

Features

Functional Description ^[1]

• Pin- and function-compatible with CY7C1019B

• High speed

The CY7C1019D is a high-performance CMOS static RAM

organized as 131,072 words by 8 bits. Easy memory

expansion is provided by an active LOW Chip Enable (CE), an

active LOW Output Enable (OE), and tri-state drivers. This

device has an automatic power-down feature that significantly

reduces power consumption when deselected. The eight input

— t_AA= 10 ns

• Low active power

— I_CC= 80 mA @ 10 ns

and output pins (IO₀through IO₇) are placed in

high-impedance state when:

• Low CMOS standby power

— I_SB2= 3 mA

• Deselected (CE HIGH)

• 2.0V Data retention

• Outputs are disabled (OE HIGH)

• Automatic power-down when deselected

• CMOS for optimum speed/power

• Center power/ground pinout

• Easy memory expansion with CE and OE options

• Functionally equivalent to CY7C1019B

• When the write operation is active (CE LOW, and WELOW).

Write to the device by taking Chip Enable (CE) and Write

Enable (WE) inputs LOW. Data on the eight IO pins (IO₀

through IO₇) is then written into the location specified on the

address pins (A₀through A₁₆).

Read from the device by taking Chip Enable (CE) and Output

Enable (OE) LOW while forcing Write Enable (WE) HIGH.

Under these conditions, the contents of the memory location

specified by the address pins appears on the IO pins.

• Available in Pb-free 32-pin 400-Mil wide Molded SOJ and

32-pin TSOP II packages

Logic Block Diagram

INPUT BUFFER

128K x 8

ARRAY

POWER

DOWN

COLUMN DECODER

Note

1. For guidelines on SRAM system design, please refer to the ‘System Design Guidelines’ Cypress application note, available on the internet at www.cypress.com.

Cypress Semiconductor Corporation

Document #: 38-05464 Rev. *F

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised December 14, 2010

[+] Feedback

12 3 4 5 6 7...13

中文翻译

下载PDF

与CY7C1019D_10相关器件

型号	品牌	获取价格	描述	数据表
CY7C1019D_11	CYPRESS	获取价格	1-Mbit (128 K × 8) Static RAM CMOS for optimu
CY7C1019D-10VXI	CYPRESS	获取价格	1-Mbit (128K x 8) Static RAM
CY7C1019D-10VXI	INFINEON	获取价格	Asynchronous SRAM
CY7C1019D-10VXIT	CYPRESS	获取价格	Standard SRAM, 128KX8, 10ns, CMOS, PDSO32, 0.400 INCH, LEAD FREE, SOJ-32
CY7C1019D-10VXIT	INFINEON	获取价格	Asynchronous SRAM
CY7C1019D-10ZSXI	CYPRESS	获取价格	1-Mbit (128K x 8) Static RAM
CY7C1019D-10ZSXIT	CYPRESS	获取价格	Standard SRAM, 128KX8, 10ns, CMOS, PDSO32,
CY7C1019D-10ZXC	CYPRESS	获取价格	Standard SRAM, 128KX8, 10ns, CMOS, PDSO32, LEAD FREE, TSOP2-32
CY7C1019D-10ZXI	CYPRESS	获取价格	Standard SRAM, 128KX8, 10ns, CMOS, PDSO32, LEAD FREE, TSOP2-32
CY7C1019D-12VXC	CYPRESS	获取价格	Standard SRAM, 128KX8, 12ns, CMOS, PDSO32, 0.400 INCH, LEAD FREE, SOJ-32

与CY7C1019D_10相关文章

国产厂商思特威CMOS图像传感器芯片单月出货超1亿颗，技术创新引领行业发展
2024-11-14

29
台积电5nm和3nm产能利用率达100%，半导体行业景气度持续攀升
2024-11-14

12
AMD宣布全球裁员约1000人，调整战略聚焦增长
2024-11-14

14
英伟达新AI芯片Rubin或提前半年亮相
2024-11-05

35

产品中心

服务支持

精选活动

关于我们

帮助中心

CY7C1019D_10

CY7C1019D_10 数据手册

与CY7C1019D_10相关器件

与CY7C1019D_10相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

CY7C1019D_10

CY7C1019D_10 数据手册

与CY7C1019D_10相关器件

与CY7C1019D_10相关文章

您还可以找

您在本页遇到什么问题？