5秒后页面跳转
捷配首页

Datasheet > CY7C1011DV33-10BVXIT
CY7C1011DV33-10BVXIT PDF预览

CY7C1011DV33-10BVXIT

更新时间： 2024-11-07 21:14:07
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 静态存储器内存集成电路
页数 文件大小 规格书
17页 404K
描述
Standard SRAM, 128KX16, 10ns, CMOS, PBGA48, 6 X 8 MM, 1 MM HEIGHT, LEAD FREE, VFBGA-48

阅读下载

中文翻译

获取价格

CY7C1011DV33-10BVXIT 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Active包装说明：VFBGA, BGA48,6X8,30
Reach Compliance Code：compliantECCN代码：3A991.B.2.B
HTS代码：8542.32.00.41Factory Lead Time：1 week
风险等级：5.51最长访问时间：10 ns
I/O 类型：COMMONJESD-30 代码：R-PBGA-B48
JESD-609代码：e1长度：8 mm
内存密度：2097152 bit内存集成电路类型：STANDARD SRAM
内存宽度：16湿度敏感等级：3
功能数量：1端子数量：48
字数：131072 words字数代码：128000
工作模式：ASYNCHRONOUS最高工作温度：85 °C
最低工作温度：-40 °C组织：128KX16
输出特性：3-STATE封装主体材料：PLASTIC/EPOXY
封装代码：VFBGA封装等效代码：BGA48,6X8,30
封装形状：RECTANGULAR封装形式：GRID ARRAY, VERY THIN PROFILE, FINE PITCH
并行/串行：PARALLEL峰值回流温度（摄氏度）：260
电源：3.3 V认证状态：Not Qualified
座面最大高度：1 mm最大待机电流：0.01 A
最小待机电流：2 V子类别：SRAMs
最大压摆率：0.09 mA最大供电电压 (Vsup)：3.6 V
最小供电电压 (Vsup)：3 V标称供电电压 (Vsup)：3.3 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子面层：Tin/Silver/Copper (Sn/Ag/Cu)
端子形式：BALL端子节距：0.75 mm
端子位置：BOTTOM处于峰值回流温度下的最长时间：30
宽度：6 mmBase Number Matches：1

CY7C1011DV33-10BVXIT 数据手册

 浏览型号CY7C1011DV33-10BVXIT的Datasheet PDF文件第2页浏览型号CY7C1011DV33-10BVXIT的Datasheet PDF文件第3页浏览型号CY7C1011DV33-10BVXIT的Datasheet PDF文件第4页浏览型号CY7C1011DV33-10BVXIT的Datasheet PDF文件第5页浏览型号CY7C1011DV33-10BVXIT的Datasheet PDF文件第6页浏览型号CY7C1011DV33-10BVXIT的Datasheet PDF文件第7页 
CY7C1011DV33  
2-Mbit (128 K × 16) Static RAM  
2-Mbit (128  
K × 16) Static RAM  
Features  
Functional Description  
■ Pin-and function-compatible with CY7C1011CV33  
The CY7C1011DV33[1] is a high-performance CMOS Static  
RAM organized as 128 K words by 16 bits.  
■ High speed  
❐ tAA = 10 ns  
Writing to the device is accomplished by taking Chip Enable (CE)  
and Write Enable (WE) inputs LOW. If Byte Low Enable (BLE) is  
LOW, then data from I/O pins (I/O0 through I/O7), is written into  
the location specified on the address pins (A0 through A16). If  
Byte High Enable (BHE) is LOW, then data from I/O pins (I/O8  
through I/O15) is written into the location specified on the address  
pins (A0 through A16).  
■ Low active power  
❐ ICC = 90 mA @ 10 ns (Industrial)  
■ Low CMOS standby power  
❐ ISB2 = 10 mA  
■ Data Retention at 2.0 V  
Reading from the device is accomplished by taking Chip Enable  
(CE) and Output Enable (OE) LOW while forcing the Write  
Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data  
from the memory location specified by the address pins will  
appear on I/O0 to I/O7. If Byte High Enable (BHE) is LOW, then  
data from memory will appear on I/O8 to I/O15. See the truth table  
at the back of this data sheet for a complete description of read  
and write modes.  
■ Automatic power-down when deselected  
■ Independent control of upper and lower bits  
■ Easy memory expansion with CE and OE features  
■ Available in Pb-free 44-pin TSOP II, and 48-ball VFBGA  
The input/output pins (I/O0 through I/O15) are placed in a  
high-impedance state when the device is deselected (CE HIGH),  
the outputs are disabled (OE HIGH), the BHE and BLE are  
disabled (BHE, BLE HIGH), or during a write operation (CE LOW,  
and WE LOW).  
The CY7C1011DV33 is available in standard Pb-free 44-pin  
TSOP II with center power and ground pinout, as well as 48-ball  
very fine-pitch ball grid array (VFBGA) packages.  
For a complete list of related resources, click here.  
Logic Block Diagram  
INPUT BUFFER  
A
0
A
1
A
2
I/O0–I/O7  
A
3
A
4
128K X 16  
I/O8–I/O15  
A
6
5
A
A
7
A
8
COLUMN  
DECODER  
BHE  
WE  
CE  
OE  
BLE  
Note  
1. For guidelines on SRAM system design, please refer to the “System Design Guidelines” Cypress application note, available on the internet at www.cypress.com  
Cypress Semiconductor Corporation  
Document Number: 38-05609 Rev. *H  
•
198 Champion Court  
•
San Jose, CA 95134-1709  
•
408-943-2600  
Revised November 12, 2014  
 
 
1234567...17

中文翻译

下载PDF

CY7C1011DV33-10BVXIT 替代型号

型号 品牌 替代类型 描述 数据表
CY7C1011DV33-10BVXI CYPRESS

类似代替

 2-Mbit (128K x 16)Static RAM
CY7C1011DV33-10BVI CYPRESS

类似代替

 2-Mbit (128K x 16)Static RAM
IS61LV12816L-10BLI ISSI

功能相似

 128K x 16 HIGH-SPEED CMOS STATIC RAM WITH 3.3V SUPPLY

与CY7C1011DV33-10BVXIT相关器件

型号 品牌 获取价格 描述 数据表
CY7C1011DV33-10ZSXI CYPRESS

获取价格

 		2-Mbit (128K x 16)Static RAM
CY7C1011DV33-10ZSXI INFINEON

获取价格

 		Asynchronous SRAM
CY7C1011DV33-10ZSXIT CYPRESS

获取价格

 		Standard SRAM, 128KX16, 10ns, CMOS, PDSO44, LEAD FREE, TSOP2-44
CY7C1011DV33-10ZSXIT INFINEON

获取价格

 		Asynchronous SRAM
CY7C1011G CYPRESS

获取价格

 		2-Mbit (128K words × 16 bit) Static RAM with
CY7C1011G30-10BAJXE CYPRESS

获取价格

 		2-Mbit (128K words × 16 bit) Static RAM with
CY7C1011G30-10BAJXE INFINEON

获取价格

 		Asynchronous SRAM
CY7C1011G30-10BAJXET INFINEON

获取价格

 		Asynchronous SRAM
CY7C1011G30-10ZSXA CYPRESS

获取价格

 		2-Mbit (128K words × 16 bit) Static RAM with
CY7C1011G30-10ZSXA INFINEON

获取价格

 		Asynchronous SRAM

与CY7C1011DV33-10BVXIT相关文章

您还可以找


热门产品
PCB打样/小批量
铝基板
BOM智能配单
PCBA制造
钣金
精密CNC
模具注塑
薄膜开关
精选活动
PCBA打样特惠
四六层板品质升级
铝基板品质升级
一体化电子制造
DFM下载
服务支持
企业认证
产品展示
工厂展示
工艺能力
积分商城
关于捷配
捷配简介
企业文化
公司动态
人才招聘
联系我们
帮助中心
下单流程
付款流程
开票流程
常见问题
全球PCB制造服务专线 400-613-0088

工作时间：9:00-21:00

CEO邮箱：ceo@jiepei.com

投诉邮箱：tousu@jiepei.com

捷配网-微信公众号 微信公众号
捷配网-微信公众号 抖音公众号
资质认证：
合作快递：
支付方式：
Copyright © 2024 Jiepei.com Inc. All Rights Reserved. 版权所有:杭州捷配信息科技有限公司 浙公网安备 33010502006866号 浙ICP备10014259号-119 营业执照ICP证