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CY7C1011DV33-10BVXI PDF预览

CY7C1011DV33-10BVXI

更新时间： 2024-11-24 05:09:31
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 内存集成电路静态存储器
页数 文件大小 规格书
11页 359K
描述
2-Mbit (128K x 16)Static RAM

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中文翻译

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CY7C1011DV33-10BVXI 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Active零件包装代码：BGA
包装说明：VFBGA, BGA48,6X8,30针数：48
Reach Compliance Code：compliantECCN代码：3A991.B.2.B
HTS代码：8542.32.00.41风险等级：1.31
最长访问时间：10 nsI/O 类型：COMMON
JESD-30 代码：R-PBGA-B48JESD-609代码：e1
长度：8 mm内存密度：2097152 bit
内存集成电路类型：STANDARD SRAM内存宽度：16
湿度敏感等级：3功能数量：1
端子数量：48字数：131072 words
字数代码：128000工作模式：ASYNCHRONOUS
最高工作温度：85 °C最低工作温度：-40 °C
组织：128KX16输出特性：3-STATE
封装主体材料：PLASTIC/EPOXY封装代码：VFBGA
封装等效代码：BGA48,6X8,30封装形状：RECTANGULAR
封装形式：GRID ARRAY, VERY THIN PROFILE, FINE PITCH并行/串行：PARALLEL
峰值回流温度（摄氏度）：260电源：3.3 V
认证状态：Not Qualified座面最大高度：1 mm
最大待机电流：0.01 A最小待机电流：2 V
子类别：SRAMs最大压摆率：0.09 mA
最大供电电压 (Vsup)：3.6 V最小供电电压 (Vsup)：3 V
标称供电电压 (Vsup)：3.3 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子面层：Tin/Silver/Copper (Sn/Ag/Cu)端子形式：BALL
端子节距：0.75 mm端子位置：BOTTOM
处于峰值回流温度下的最长时间：30宽度：6 mm
Base Number Matches：1

CY7C1011DV33-10BVXI 数据手册

 浏览型号CY7C1011DV33-10BVXI的Datasheet PDF文件第2页浏览型号CY7C1011DV33-10BVXI的Datasheet PDF文件第3页浏览型号CY7C1011DV33-10BVXI的Datasheet PDF文件第4页浏览型号CY7C1011DV33-10BVXI的Datasheet PDF文件第5页浏览型号CY7C1011DV33-10BVXI的Datasheet PDF文件第6页浏览型号CY7C1011DV33-10BVXI的Datasheet PDF文件第7页 
CY7C1011DV33  
2-Mbit (128K x 16)Static RAM  
Features  
Functional Description  
• Pin-and function-compatible with CY7C1011CV33  
• High speed  
The CY7C1011DV33 is a high-performance CMOS Static  
RAM organized as 128K words by 16 bits.  
Writing to the device is accomplished by taking Chip Enable  
(CE) and Write Enable (WE) inputs LOW. If Byte Low Enable  
(BLE) is LOW, then data from I/O pins (I/O0 through I/O7), is  
written into the location specified on the address pins (A0  
through A16). If Byte High Enable (BHE) is LOW, then data  
from I/O pins (I/O8 through I/O15) is written into the location  
specified on the address pins (A0 through A16).  
— tAA = 10 ns  
• Low active power  
— ICC = 90 mA @ 10 ns (Industrial)  
• Low CMOS standby power  
— ISB2 = 10 mA  
• Data Retention at 2.0 V  
Reading from the device is accomplished by taking Chip  
Enable (CE) and Output Enable (OE) LOW while forcing the  
Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW,  
then data from the memory location specified by the address  
pins will appear on I/O0 to I/O7. If Byte High Enable (BHE) is  
LOW, then data from memory will appear on I/O8 to I/O15. See  
the truth table at the back of this data sheet for a complete  
description of read and write modes.  
• Automatic power-down when deselected  
• Independent control of upper and lower bits  
• Easy memory expansion with CE and OE features  
• Available in Lead-Free 44-pin TSOP II, and 48-ball VFBGA  
The input/output pins (I/O0 through I/O15) are placed in a  
high-impedance state when the device is deselected (CE  
HIGH), the outputs are disabled (OE HIGH), the BHE and BLE  
are disabled (BHE, BLE HIGH), or during a write operation (CE  
LOW, and WE LOW).  
The CY7C1011DV33 is available in standard Lead-Free  
44-pin TSOP II with center power and ground pinout, as well  
as 48-ball fine-pitch ball grid array (VFBGA) packages  
.
Pin Configuration  
TSOP II  
Logic Block Diagram  
Top View  
INPUT BUFFER  
44  
1
A
4
A
5
43  
42  
41  
40  
39  
38  
A
A
2
3
4
5
6
3
6
A
0
A
A
2
7
A
1
OE  
A
1
A
2
BHE  
BLE  
I/O  
I/O  
I/O  
A
I/O0–I/O7  
0
A
3
CE  
A
4
128K X 16  
I/O  
7
0
15  
I/O8–I/O15  
A
5
37  
36  
35  
34  
33  
I/O  
I/O  
8
A
1
2
14  
6
9
A
13  
7
10  
11  
12  
13  
A
I/O  
V
SS  
I/O  
8
3
CC  
12  
V
SS  
V
V
CC  
32  
I/O  
I/O  
4
5
6
7
11  
10  
COLUMN  
DECODER  
31  
30  
29  
28  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
14  
15  
16  
9
8
WE 17  
NC  
A
18  
16  
15  
27  
26  
25  
A
8
A
BHE  
19  
20  
21  
22  
A
9
10  
11  
WE  
CE  
OE  
A
14  
A
A
A
12  
24  
23  
13  
A
NC  
BLE  
Note  
1. For guidelines on SRAM system design, please refer to the “System Design Guidelines” Cypress application note, available on the internet at www.cypress.com  
Cypress Semiconductor Corporation  
Document #: 38-05609 Rev. *C  
•
198 Champion Court  
•
San Jose, CA 95134-1709  
•
408-943-2600  
Revised July 14, 2006  
[+] Feedback  
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中文翻译

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CY7C1011DV33-10BVXI 替代型号

型号 品牌 替代类型 描述 数据表
CY7C1011DV33-10BVI CYPRESS

完全替代

 2-Mbit (128K x 16)Static RAM
CY7C1011DV33-10BVXIT CYPRESS

类似代替

 Standard SRAM, 128KX16, 10ns, CMOS, PBGA48, 6 X 8 MM, 1 MM HEIGHT, LEAD FREE, VFBGA-48
IS61LV12816L-10BLI ISSI

功能相似

 128K x 16 HIGH-SPEED CMOS STATIC RAM WITH 3.3V SUPPLY

与CY7C1011DV33-10BVXI相关器件

型号 品牌 获取价格 描述 数据表
CY7C1011DV33-10BVXIT CYPRESS

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 		Standard SRAM, 128KX16, 10ns, CMOS, PBGA48, 6 X 8 MM, 1 MM HEIGHT, LEAD FREE, VFBGA-48
CY7C1011DV33-10BVXIT INFINEON

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 		Asynchronous SRAM
CY7C1011DV33-10ZSXI CYPRESS

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 		2-Mbit (128K x 16)Static RAM
CY7C1011DV33-10ZSXI INFINEON

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 		Asynchronous SRAM
CY7C1011DV33-10ZSXIT CYPRESS

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 		Standard SRAM, 128KX16, 10ns, CMOS, PDSO44, LEAD FREE, TSOP2-44
CY7C1011DV33-10ZSXIT INFINEON

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 		Asynchronous SRAM
CY7C1011G CYPRESS

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 		2-Mbit (128K words × 16 bit) Static RAM with
CY7C1011G30-10BAJXE CYPRESS

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 		2-Mbit (128K words × 16 bit) Static RAM with
CY7C1011G30-10BAJXE INFINEON

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 		Asynchronous SRAM
CY7C1011G30-10BAJXET INFINEON

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 		Asynchronous SRAM

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