Datasheet > CY7C1011DV33-10ZSXIT

CY7C1011DV33-10ZSXIT

更新时间： 2024-11-08 14:53:51

品牌	Logo	应用领域
英飞凌 - INFINEON		静态存储器
页数	文件大小	规格书
17页	499K
描述
Asynchronous SRAM

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CY7C1011DV33-10ZSXIT 数据手册

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CY7C1011DV33

2-Mbit (128 K × 16) Static RAM

2-Mbit (128

K × 16) Static RAM

Features

Functional Description

■ Pin-and function-compatible with CY7C1011CV33

The CY7C1011DV33^[1]is a high-performance CMOS Static

RAM organized as 128 K words by 16 bits.

■ High speed

❐ t_AA= 10 ns

Writing to the device is accomplished by taking Chip Enable (CE)

and Write Enable (WE) inputs LOW. If Byte Low Enable (BLE) is

LOW, then data from I/O pins (I/O₀through I/O₇), is written into

the location specified on the address pins (A₀through A₁₆). If

Byte High Enable (BHE) is LOW, then data from I/O pins (I/O₈

through I/O₁₅) is written into the location specified on the address

pins (A₀through A₁₆).

■ Low active power

❐ I_CC= 90 mA @ 10 ns (Industrial)

■ Low CMOS standby power

❐ I_SB2= 10 mA

■ Data Retention at 2.0 V

Reading from the device is accomplished by taking Chip Enable

(CE) and Output Enable (OE) LOW while forcing the Write

Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data

from the memory location specified by the address pins will

appear on I/O₀to I/O₇. If Byte High Enable (BHE) is LOW, then

data from memory will appear on I/O₈to I/O₁₅. See the truth table

at the back of this data sheet for a complete description of read

and write modes.

■ Automatic power-down when deselected

■ Independent control of upper and lower bits

■ Easy memory expansion with CE and OE features

■ Available in Pb-free 44-pin TSOP II, and 48-ball VFBGA

The input/output pins (I/O₀through I/O₁₅) are placed in a

high-impedance state when the device is deselected (CE HIGH),

the outputs are disabled (OE HIGH), the BHE and BLE are

disabled (BHE, BLE HIGH), or during a write operation (CE LOW,

and WE LOW).

The CY7C1011DV33 is available in standard Pb-free 44-pin

TSOP II with center power and ground pinout, as well as 48-ball

very fine-pitch ball grid array (VFBGA) packages.

For a complete list of related resources, click here.

Logic Block Diagram

INPUT BUFFER

I/O₀–I/O₇

128K X 16

I/O₈–I/O₁₅

COLUMN

DECODER

BHE

BLE

Note

1. For guidelines on SRAM system design, please refer to the “System Design Guidelines” Cypress application note, available on the internet at www.cypress.com

Cypress Semiconductor Corporation

Document Number: 38-05609 Rev. *H

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised November 12, 2014

12 3 4 5 6 7...17

中文翻译

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与CY7C1011DV33-10ZSXIT相关器件

型号	品牌	获取价格	描述	数据表
CY7C1011G	CYPRESS	获取价格	2-Mbit (128K words Ã 16 bit) Static RAM with
CY7C1011G30-10BAJXE	CYPRESS	获取价格	2-Mbit (128K words Ã 16 bit) Static RAM with
CY7C1011G30-10BAJXE	INFINEON	获取价格	Asynchronous SRAM
CY7C1011G30-10BAJXET	INFINEON	获取价格	Asynchronous SRAM
CY7C1011G30-10ZSXA	CYPRESS	获取价格	2-Mbit (128K words Ã 16 bit) Static RAM with
CY7C1011G30-10ZSXA	INFINEON	获取价格	Asynchronous SRAM
CY7C1011G30-10ZSXAT	INFINEON	获取价格	Asynchronous SRAM
CY7C1011G30-10ZSXE	CYPRESS	获取价格	2-Mbit (128K words Ã 16 bit) Static RAM with
CY7C1011G30-12ZSXE	INFINEON	获取价格	Asynchronous SRAM
CY7C1011G30-12ZSXET	INFINEON	获取价格	Asynchronous SRAM

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