Datasheet > CY7C1011G

CY7C1011G

更新时间： 2024-11-10 01:09:15

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		/
页数	文件大小	规格书
17页	578K
描述
2-Mbit (128K words Ã 16 bit) Static RAM with Error-Correcting Code (ECC)

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CY7C1011G 数据手册

CY7C1011G Automotive

2-Mbit (128K words × 16 bit) Static RAM

with Error-Correcting Code (ECC)

2-Mbit (128K words

× 16 bit) Static RAM with Error-Correcting Code (ECC)

Features

Functional Description

CY7C1011G is a high-performance CMOS fast static RAM

automotive part with embedded ECC. This device has a single

Chip Enable (CE) input, and is accessed by asserting it LOW.

■ High speed

❐ t_AA= 10 ns

■ Temperature range

❐ Automotive-A: –40 °C to 85 °C

❐ Automotive-E: –40 °C to 125 °C

To perform data writes, assert the Write Enable (WE) input LOW,

and provide the data on the device data pins (I/O₀through I/O₁₅

)

and address pins (A₀through A₁₆) pins. The Byte High Enable

(BHE) and Byte Low Enable (BLE) inputs control byte writes and

write data on the corresponding I/O lines to the memory location

specified. BHE controls I/O₈through I/O₁₅and BLE controls I/O₀

through I/O₇.

■ Embedded error-correcting code (ECC) for single-bit error

correction^[1]

■ Low active and standby current

❐ Active current, I_CC= 40-mA typical (Automotive-E)

❐ Standby current, I_SB2= 6-mA typical (Automotive-E)

To perform data reads, assert the Output Enable (OE) input and

provide the required address on the address lines. You can

access read data on the I/O lines (I/O₀through I/O₁₅). To perform

byte access, assert the required byte enable signal (BHE or BLE)

to read either the upper byte or the lower byte of data from the

specified address location.

■ Operating voltage range: 2.2 V to 3.6 V

■ 1.0-V data retention

■ TTL compatible inputs and outputs

■ Available in Pb-free 48-ball VFBGA and 44-pin TSOP II

All I/Os (I/O₀through I/O₁₅) are placed in a high-impedance state

when the device is deselected (CE LOW), or when the control

signals are deasserted (OE, BLE, BHE).

packages

Logic Block Diagram – CY7C1011G

ECC ENCODER

INPUT BUFFER

I/O₀‐I/O₇

I/O₈‐I/O₁₅

MEMORY

ARRAY

COLUMN DECODER

BHE

BLE

Note

1. This device does not support automatic write-back on error detection.

Cypress Semiconductor Corporation

Document Number: 001-95423 Rev. *B

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised November 23, 2015

12 3 4 5 6 7...17

中文翻译

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与CY7C1011G相关器件

型号	品牌	获取价格	描述	数据表
CY7C1011G30-10BAJXE	CYPRESS	获取价格	2-Mbit (128K words Ã 16 bit) Static RAM with
CY7C1011G30-10BAJXE	INFINEON	获取价格	Asynchronous SRAM
CY7C1011G30-10BAJXET	INFINEON	获取价格	Asynchronous SRAM
CY7C1011G30-10ZSXA	CYPRESS	获取价格	2-Mbit (128K words Ã 16 bit) Static RAM with
CY7C1011G30-10ZSXA	INFINEON	获取价格	Asynchronous SRAM
CY7C1011G30-10ZSXAT	INFINEON	获取价格	Asynchronous SRAM
CY7C1011G30-10ZSXE	CYPRESS	获取价格	2-Mbit (128K words Ã 16 bit) Static RAM with
CY7C1011G30-12ZSXE	INFINEON	获取价格	Asynchronous SRAM
CY7C1011G30-12ZSXET	INFINEON	获取价格	Asynchronous SRAM
CY7C101-25DC	ETC	获取价格	x4 SRAM

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