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CY7C1009V33L-12VC PDF预览

CY7C1009V33L-12VC

更新时间： 2024-11-09 02:51:23
品牌 Logo 应用领域
赛普拉斯 - CYPRESS /
页数 文件大小 规格书
9页 201K
描述
128K x 8 Static RAM

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中文翻译

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CY7C1009V33L-12VC 数据手册

 浏览型号CY7C1009V33L-12VC的Datasheet PDF文件第2页浏览型号CY7C1009V33L-12VC的Datasheet PDF文件第3页浏览型号CY7C1009V33L-12VC的Datasheet PDF文件第4页浏览型号CY7C1009V33L-12VC的Datasheet PDF文件第5页浏览型号CY7C1009V33L-12VC的Datasheet PDF文件第6页浏览型号CY7C1009V33L-12VC的Datasheet PDF文件第7页 
CY7C1009V33  
CY7C109V33  
128K x 8 Static RAM  
memory expansion is provided by an active LOW Chip Enable  
Features  
(CE ), an active HIGH Chip Enable (CE ), an active LOW Out-  
1
2
• High speed  
put Enable (OE), and three-state drivers. Writing to the device  
is accomplished by taking Chip Enable one (CE ) and Write  
1
— t = 15, 20, 25ns  
AA  
Enable (WE) inputs LOW and Chip Enable two (CE ) input  
2
• V = 3.3V ± 10%  
CC  
HIGH. Data on the eight I/O pins (I/O through I/O ) is then  
0
7
• Low active power  
— 432 mW (max.)  
written into the location specified on the address pins (A  
0
through A ).  
16  
Reading from the device is accomplished by taking Chip En-  
able one (CE ) and Output Enable (OE) LOW while forcing  
— 288 mW (L version)  
• Low CMOS standby power  
— 18 mW (max.)  
1
Write Enable (WE) and Chip Enable two (CE ) HIGH. Under  
2
these conditions, the contents of the memory location speci-  
fied by the address pins will appear on the I/O pins.  
— 7.2 mW (L version)  
• 2.0V Data Retention  
The eight input/output pins (I/O through I/O ) are placed in a  
0
7
high-impedance state when the device is deselected (CE  
• Automatic power-down when deselected  
• TTL-compatible inputs and outputs  
1
HIGH or CE LOW), the outputs are disabled (OE HIGH), or  
2
during a write operation (CE LOW, CE HIGH, and WE LOW).  
1
2
• Easy memory expansion with CE , CE , and OE options  
1
2
The CY7C109V33 is available in standard 32-pin,  
400-mil-wide SOJ package. The CY7C1009V33 is available in  
a 32-pin, 300-mil-wide SOJ package. The CY7C1009V33 and  
CY7C109V33 are functionally equivalent in all other respects.  
Functional Description  
The CY7C109V33/CY7C1009V33 is a high-performance  
CMOS static RAM organized as 131,072 words by 8 bits. Easy  
Logic Block Diagram  
Pin Configurations  
SOJ  
Top View  
V
NC  
32  
31  
30  
1
CC  
A
16  
A
14  
A
12  
A
15  
2
3
4
CE  
2
29  
28  
WE  
5
A
A
A
A
7
13  
27  
26  
A
6
6
8
A
5
7
9
25  
24  
23  
22  
21  
A
A
3
8
9
10  
11  
12  
13  
4
A
11  
OE  
I/O  
0
A
A
10  
2
INPUT BUFFER  
A
1
CE  
1
I/O  
7
A
0
I/O  
I/O  
1
2
I/O  
0
I/O  
1
I/O  
2
I/O  
6
20  
19  
A
0
I/O  
5
14  
15  
16  
A
1
I/O  
I/O  
4
18  
17  
A
2
GND  
3
A
4
109V33–2  
32  
3
A
A
A
A
I/O  
I/O  
I/O  
1
2
OE  
11  
3
4
5
512 x 256 x 8  
ARRAY  
A
31  
30  
29  
28  
27  
26  
25  
24  
23  
22  
21  
20  
19  
18  
17  
A
5
6
9
8
10  
3
4
5
6
7
8
CE  
A
A
13  
I/O  
7
A
7
8
WE  
CE  
2
I/O  
6
I/O  
5
A
A
15  
I/O  
TSOP I  
4
3
V
I/O  
Top View  
CC  
NC  
9
GND  
(not to scale)  
A
16  
I/O  
2
10  
11  
12  
13  
14  
15  
16  
I/O  
I/O  
6
7
I/O  
1
A
12  
POWER  
DOWN  
14  
COLUMN  
DECODER  
A
I/O  
A
0
0
CE  
2
1
CE  
A
A
6
A
A
7
A
1
WE  
A
2
5
4
A
3
109V33–1  
OE  
109V33–3  
Selection Guide  
7C109V33-12 7C109V33-15 7C109V33-20 7C109V33-25  
7C1009V33-12 7C1009V33-15 7C1009V33-20 7C1009V33-25  
Maximum Access Time (ns)  
Maximum Operating Current (mA)  
Maximum Operating Current (mA) Low Power Version  
Maximum CMOS Standby Current (mA) Standard  
12  
130  
90  
5
15  
120  
80  
5
20  
110  
70  
5
20  
110  
70  
5
Maximum CMOS Standby Current (mA) Low Power Version  
Shaded areas contain preliminary information.  
2
2
2
2
Cypress Semiconductor Corporation  
•
3901 North First Street  
•
San Jose  
•
CA 95134  
•
408-943-2600  
September 3, 1999  
1234567...9

中文翻译

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