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CY7C09359V-7AC PDF预览

CY7C09359V-7AC

更新时间: 2024-11-07 14:48:43
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 静态存储器内存集成电路
页数 文件大小 规格书
15页 552K
描述
Dual-Port SRAM, 8KX18, 7.5ns, CMOS, PQFP100, PLASTIC, TQFP-100

CY7C09359V-7AC 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Obsolete零件包装代码:QFP
包装说明:PLASTIC, TQFP-100针数:100
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.32.00.41风险等级:5.91
最长访问时间:7.5 ns其他特性:AUTOMATIC POWER DOWN
I/O 类型:COMMONJESD-30 代码:S-PQFP-G100
JESD-609代码:e0长度:14 mm
内存密度:147456 bit内存集成电路类型:DUAL-PORT SRAM
内存宽度:18湿度敏感等级:3
功能数量:1端口数量:2
端子数量:100字数:8192 words
字数代码:8000工作模式:SYNCHRONOUS
最高工作温度:70 °C最低工作温度:
组织:8KX18输出特性:3-STATE
封装主体材料:PLASTIC/EPOXY封装代码:LFQFP
封装等效代码:QFP100,.63SQ,20封装形状:SQUARE
封装形式:FLATPACK, LOW PROFILE, FINE PITCH并行/串行:PARALLEL
峰值回流温度(摄氏度):240电源:3.3 V
认证状态:Not Qualified座面最大高度:1.6 mm
最大待机电流:0.00005 A最小待机电流:3 V
子类别:SRAMs最大压摆率:0.275 mA
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):3 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子面层:Tin/Lead (Sn/Pb)端子形式:GULL WING
端子节距:0.5 mm端子位置:QUAD
处于峰值回流温度下的最长时间:30宽度:14 mm
Base Number Matches:1

CY7C09359V-7AC 数据手册

 浏览型号CY7C09359V-7AC的Datasheet PDF文件第2页浏览型号CY7C09359V-7AC的Datasheet PDF文件第3页浏览型号CY7C09359V-7AC的Datasheet PDF文件第4页浏览型号CY7C09359V-7AC的Datasheet PDF文件第5页浏览型号CY7C09359V-7AC的Datasheet PDF文件第6页浏览型号CY7C09359V-7AC的Datasheet PDF文件第7页 
51  
fax id: 5209  
CY7C09349V  
CY7C09359V  
PRELIMINARY  
3.3V 4K/8K x 18  
Synchronous Dual-Port Static RAM  
• High-speed clock to data access 7.5/12 ns (max.)  
• 3.3V Low operating power  
Features  
• True Dual-Ported memory cells which allow simulta-  
neous access of the same memory location  
— Active= 135 mA (typical)  
— Standby= 10 A (typical)  
µ
• 2 Flow-Through/Pipelined devices  
— 4K x 18 organization (CY7C09349V)  
— 8K x 18 organization (CY7C09359V)  
• 3 Modes  
• Fully synchronous interface for easier operation  
• Burst counters increment addresses internally  
— Shorten cycle times  
— Minimize bus noise  
— Flow-Through  
— Supported in Flow-Through and Pipelined modes  
• Dual Chip Enables for easy depth expansion  
• Upper and lower byte controls for bus matching  
• Automatic power-down  
— Pipelined  
— Burst  
• Pipelinedoutputmodeonboth portsallowsfast67-MHz  
operation  
• Commercial and Industrial temperature ranges  
• 0.35-micron CMOS for optimum speed/power  
Available in 100-pin TQFP  
v
Logic Block Diagram  
R/W  
R/W  
UB  
L
R
R
UB  
L
CE  
CE  
CE  
CE  
0L  
1L  
0R  
1R  
1
1
0
0
0/1  
0/1  
LB  
LB  
L
R
R
OE  
OE  
L
1b 0b 1a 0a  
0a 1a 0b 1b  
0/1  
0/1  
b
a
a
b
FT/Pipe  
FT/Pipe  
L
R
9
9
9
9
I/O –I/O  
I/O –I/O  
9R 17R  
9L  
17L  
8L  
I/O  
Control  
I/O  
Control  
I/O –I/O  
I/O –I/O  
0L  
0R  
8R  
12/13  
12/13  
[1]  
A
–A[1]  
A
–A  
0L  
11/12L  
0R 11/12R  
Counter/  
Address  
Register  
Decode  
Counter/  
Address  
Register  
Decode  
CLK  
CLK  
ADS  
L
R
R
R
R
True Dual-Ported  
RAM Array  
ADS  
L
CNTEN  
CNTEN  
L
CNTRST  
CNTRST  
L
Note:  
1. A0–A11 for 4K; A0–A12 for 8K devices.  
For the most recent information, visit the Cypress web site at www.cypress.com  
Cypress Semiconductor Corporation  
3901 North First Street  
San Jose  
CA 95134  
408-943-2600  
November 7, 1997 - Revised June 5, 1998  

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