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CY7C09369V-9AI PDF预览

CY7C09369V-9AI

更新时间: 2024-02-05 23:17:24
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 存储内存集成电路静态存储器时钟
页数 文件大小 规格书
19页 348K
描述
3.3V 16K/32K/64K x 16/18 Synchronous Dual-Port Static RAM

CY7C09369V-9AI 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:QFP
包装说明:ROHS COMPLIANT, PLASTIC, MS-026, TQFP-100针数:100
Reach Compliance Code:unknownECCN代码:3A991.B.2.B
HTS代码:8542.32.00.41风险等级:5.62
Is Samacsys:N最长访问时间:9 ns
其他特性:FLOW-THROUGH OR PIPELINED ARCHITECTURE最大时钟频率 (fCLK):67 MHz
I/O 类型:COMMONJESD-30 代码:S-PQFP-G100
JESD-609代码:e4长度:14 mm
内存密度:294912 bit内存集成电路类型:DUAL-PORT SRAM
内存宽度:18湿度敏感等级:3
功能数量:1端口数量:2
端子数量:100字数:16384 words
字数代码:16000工作模式:SYNCHRONOUS
最高工作温度:70 °C最低工作温度:
组织:16KX18输出特性:3-STATE
封装主体材料:PLASTIC/EPOXY封装代码:LFQFP
封装等效代码:QFP100,.63SQ,20封装形状:SQUARE
封装形式:FLATPACK, LOW PROFILE, FINE PITCH并行/串行:PARALLEL
峰值回流温度(摄氏度):260电源:3.3 V
认证状态:Not Qualified座面最大高度:1.6 mm
最大待机电流:0.00025 A最小待机电流:3 V
子类别:SRAMs最大压摆率:0.23 mA
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):3 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)端子形式:GULL WING
端子节距:0.5 mm端子位置:QUAD
处于峰值回流温度下的最长时间:20宽度:14 mm
Base Number Matches:1

CY7C09369V-9AI 数据手册

 浏览型号CY7C09369V-9AI的Datasheet PDF文件第2页浏览型号CY7C09369V-9AI的Datasheet PDF文件第3页浏览型号CY7C09369V-9AI的Datasheet PDF文件第4页浏览型号CY7C09369V-9AI的Datasheet PDF文件第5页浏览型号CY7C09369V-9AI的Datasheet PDF文件第6页浏览型号CY7C09369V-9AI的Datasheet PDF文件第7页 
25/0251  
CY7C09269V/79V/89V  
CY7C09369V/79V/89V  
3.3V 16K/32K/64K x 16/18  
Synchronous Dual-Port Static RAM  
• High-speed clock to data access 6.5[1, 2]/7.5[2]/9/12 ns  
(max.)  
Features  
• True Dual-Ported memory cells which allow simulta-  
neous access of the same memory location  
• 3.3V low operating power  
Active = 115 mA (typical)  
• 6 Flow-Through/Pipelined devices  
— 16K x 16/18 organization (CY7C09269V/369V)  
— 32K x 16/18 organization (CY7C09279V/379V)  
— 64K x 16/18 organization (CY7C09289V/389V)  
• 3 Modes  
Standby = 10 µA (typical)  
• Fully synchronous interface for easier operation  
• Burst counters increment addresses internally  
Shorten cycle times  
Minimize bus noise  
— Flow-Through  
Supported in Flow-Through and Pipelined modes  
• Dual Chip Enables for easy depth expansion  
• Upper and Lower Byte Controls for Bus Matching  
• Automatic power-down  
• Commercial and Industrial temperature ranges  
• Available in 100-pin TQFP  
— Pipelined  
— Burst  
• Pipelined output mode on both ports allows fast  
100-MHz operation  
• 0.35-micron CMOS for optimum speed/power  
Logic Block Diagram  
R/WL  
UBL  
R/WR  
UBR  
CE0L  
CE0R  
1
1
CE1L  
LBL  
CE1R  
LBR  
0
0
0/1  
0/1  
OEL  
OER  
1b 0b 1a 0a  
0a 1a 0b 1b  
0/1  
0/1  
b
a
a
b
FT/PipeL  
FT/PipeR  
8/9  
8/9  
8/9  
8/9  
[3]  
[3]  
I/O8/9LI/O15/17L  
I/O8/9RI/O15/17R  
I/O  
Control  
I/O  
Control  
[4]  
[4]  
I/O0LI/O  
I/O0RI/O  
7/8L  
7/8R  
14/15/16  
14/15/16  
[5]  
[5]  
A0LA  
A
A  
13/14/15L  
0R  
13/14/15R  
CLKR  
Counter/  
Address  
Register  
Decode  
Counter/  
Address  
Register  
Decode  
CLKL  
ADSL  
True Dual-Ported  
RAM Array  
ADSR  
CNTENL  
CNTENR  
CNTRSTL  
CNTRSTR  
Notes:  
1. Call for availability.  
2. See page 6 for Load Conditions.  
3. I/O8I/O15 for x16 devices; I/O9I/O17 for x18 devices.  
4. I/O0I/O7 for x16 devices. I/O0I/O8 for x18 devices.  
5. A0A13 for 16K; A0A14 for 32K; A0A15 for 64K devices.  
For the most recent information, visit the Cypress web site at www.cypress.com  
Cypress Semiconductor Corporation  
3901 North First Street  
San Jose  
CA 95134  
408-943-2600  
Document #: 38-06056 Rev. **  
Revised September 21, 2001  

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