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CY7C09369A-9AC PDF预览

CY7C09369A-9AC

更新时间: 2024-11-09 00:01:31
品牌 Logo 应用领域
赛普拉斯 - CYPRESS /
页数 文件大小 规格书
18页 345K
描述
16K x16/18 Synchronous Dual Port Static RAM

CY7C09369A-9AC 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:QFP包装说明:PLASTIC, TQFP-100
针数:100Reach Compliance Code:not_compliant
ECCN代码:3A991.B.2.BHTS代码:8542.32.00.41
风险等级:5.83最长访问时间:20 ns
其他特性:FLOW-THROUGH OR PIPELINED ARCHITECTURE最大时钟频率 (fCLK):67 MHz
I/O 类型:COMMONJESD-30 代码:S-PQFP-G100
JESD-609代码:e0长度:14 mm
内存密度:294912 bit内存集成电路类型:DUAL-PORT SRAM
内存宽度:18功能数量:1
端口数量:2端子数量:100
字数:16384 words字数代码:16000
工作模式:SYNCHRONOUS最高工作温度:70 °C
最低工作温度:组织:16KX18
输出特性:3-STATE封装主体材料:PLASTIC/EPOXY
封装代码:LFQFP封装等效代码:QFP100,.63SQ,20
封装形状:SQUARE封装形式:FLATPACK, LOW PROFILE, FINE PITCH
并行/串行:PARALLEL峰值回流温度(摄氏度):NOT SPECIFIED
电源:5 V认证状态:Not Qualified
座面最大高度:1.6 mm最大待机电流:0.0005 A
最小待机电流:4.5 V子类别:SRAMs
最大压摆率:0.36 mA最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子面层:Tin/Lead (Sn/Pb)
端子形式:GULL WING端子节距:0.5 mm
端子位置:QUAD处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:14 mmBase Number Matches:1

CY7C09369A-9AC 数据手册

 浏览型号CY7C09369A-9AC的Datasheet PDF文件第2页浏览型号CY7C09369A-9AC的Datasheet PDF文件第3页浏览型号CY7C09369A-9AC的Datasheet PDF文件第4页浏览型号CY7C09369A-9AC的Datasheet PDF文件第5页浏览型号CY7C09369A-9AC的Datasheet PDF文件第6页浏览型号CY7C09369A-9AC的Datasheet PDF文件第7页 
25/0251  
CY7C09269A  
CY7C09369A  
16K x16/18 Synchronous  
Dual Port Static RAM  
• Low operating power  
Features  
Active = 195 mA (typical)  
• True dual-ported memory cells which allow simulta-  
neous access of the same memory location  
Standby = 0.05 mA (typical)  
• Fully synchronous interface for easier operation  
• Burst counters increment addresses internally  
Shorten cycle times  
• Two Flow-Through/Pipelined devices  
— 16K x 16/18 organization (CY7C09269A/369A)  
• Three Modes  
Minimize bus noise  
— Flow-Through  
Supported in Flow-Through and Pipelined modes  
• Dual Chip Enables for easy depth expansion  
• Upper and Lower Byte Controls for Bus Matching  
• Automatic power-down  
— Pipelined  
— Burst  
• Pipelined output mode on both ports allows fast 100-  
MHz cycle time  
• 0.35-micron CMOS for optimum speed/power  
• High-speedclocktodataaccess6.5[1]/7.5/9/12ns(max.)  
• Commercial temperature range  
• Available in 100-pin TQFP  
• Pin-compatible and functionally equivalent to  
IDT709269  
Logic Block Diagram  
R/WL  
UBL  
R/WR  
UBR  
CE0L  
CE0R  
1
1
CE1L  
LBL  
CE1R  
LBR  
0
0
0/1  
0/1  
OEL  
OER  
1b 0b 1a 0a  
0a 1a 0b 1b  
0/1  
0/1  
b
a
a
b
FT/PipeL  
FT/PipeR  
8/9  
8/9  
8/9  
8/9  
[2]  
[2]  
I/O8/9LI/O15/17L  
I/O8/9RI/O15/17R  
I/O  
Control  
I/O  
Control  
[3]  
[3]  
I/O0LI/O  
I/O0RI/O  
7/8L  
7/8R  
14  
14  
A
0LA13L  
A0RA13R  
Counter/  
Address  
Register  
Decode  
Counter/  
Address  
Register  
Decode  
CLKL  
CLKR  
ADSR  
True Dual-Ported  
RAM Array  
ADSL  
CNTENL  
CNTENR  
CNTRSTR  
CNTRSTL  
Notes:  
1. See page 6 for Load Conditions.  
2. I/O8I/O15 for x16 devices; I/O9I/O17 for x18 devices.  
3. I/O0I/O7 for x16 devices. I/O0I/O8 for x18 devices.  
For the most recent information, visit the Cypress web site at www.cypress.com  
Cypress Semiconductor Corporation  
3901 North First Street  
San Jose  
CA 95134  
408-943-2600  
Document #: 38-06050 Rev. *A  
Revised December 27, 2002  

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