25/0251
CY7C09269V/79V/89V
CY7C09369V/79V/89V
3.3V 16K/32K/64K x 16/18
Synchronous Dual-Port Static RAM
• High-speed clock to data access 6.5[1, 2]/7.5[2]/9/12 ns
(max.)
Features
• True Dual-Ported memory cells which allow simulta-
neous access of the same memory location
• 3.3V low operating power
—Active = 115 mA (typical)
• 6 Flow-Through/Pipelined devices
— 16K x 16/18 organization (CY7C09269V/369V)
— 32K x 16/18 organization (CY7C09279V/379V)
— 64K x 16/18 organization (CY7C09289V/389V)
• 3 Modes
—Standby = 10 µA (typical)
• Fully synchronous interface for easier operation
• Burst counters increment addresses internally
—Shorten cycle times
—Minimize bus noise
— Flow-Through
—Supported in Flow-Through and Pipelined modes
• Dual Chip Enables for easy depth expansion
• Upper and Lower Byte Controls for Bus Matching
• Automatic power-down
• Commercial and Industrial temperature ranges
• Available in 100-pin TQFP
— Pipelined
— Burst
• Pipelined output mode on both ports allows fast
100-MHz operation
• 0.35-micron CMOS for optimum speed/power
Logic Block Diagram
R/WL
UBL
R/WR
UBR
CE0L
CE0R
1
1
CE1L
LBL
CE1R
LBR
0
0
0/1
0/1
OEL
OER
1b 0b 1a 0a
0a 1a 0b 1b
0/1
0/1
b
a
a
b
FT/PipeL
FT/PipeR
8/9
8/9
8/9
8/9
[3]
[3]
I/O8/9L–I/O15/17L
I/O8/9R–I/O15/17R
I/O
Control
I/O
Control
[4]
[4]
I/O0L–I/O
I/O0R–I/O
7/8L
7/8R
14/15/16
14/15/16
[5]
[5]
A0L–A
A
–A
13/14/15L
0R
13/14/15R
CLKR
Counter/
Address
Register
Decode
Counter/
Address
Register
Decode
CLKL
ADSL
True Dual-Ported
RAM Array
ADSR
CNTENL
CNTENR
CNTRSTL
CNTRSTR
Notes:
1. Call for availability.
2. See page 6 for Load Conditions.
3. I/O8–I/O15 for x16 devices; I/O9–I/O17 for x18 devices.
4. I/O0–I/O7 for x16 devices. I/O0–I/O8 for x18 devices.
5. A0–A13 for 16K; A0–A14 for 32K; A0–A15 for 64K devices.
For the most recent information, visit the Cypress web site at www.cypress.com
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
Document #: 38-06056 Rev. **
Revised September 21, 2001