Datasheet > CY7C09369V

CY7C09369V

更新时间： 2022-04-23 23:00:11

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		/
页数	文件大小	规格书
19页	348K
描述
3.3V 16K/32K/64K x 16/18 Synchronous Dual-Port Static RAM

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中文翻译

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数据手册

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CY7C09369V 数据手册

CY7C09269V/79V/89V

CY7C09369V/79V/89V

Electrical Characteristics Over the Operating Range

CY7C09269V/79V/89V

CY7C09369V/79V/89V

-6^{[1, 2]}

-7^[2]

-9

-12

Parameter

Description

V_OH

Output HIGH Voltage (V_CC= Min.

l_OH= –4.0 mA)

2.4

2.0

2.4

2.0

V_OL

Output LOW Voltage (V_CC= Min.

l_OH= +4.0 mA)

0.4

0.8

0.4

0.8

0.4

0.8

0.4

0.8

V_IH

V_IL

I_OZ

I_CC

Input HIGH Voltage

Input LOW Voltage

2.0

Output Leakage Current

–10

10 –10

10 µA

Operating Current

Com’l.

175 320

155 275

275 390

135 230

185 300

115 180 mA

(V_CC= Max, I_OUT= 0 mA)

Outputs Disabled

Indust.

I_SB1

I_SB2

I_SB3

I_SB4

Standby Current (Both

Ports TTL Level)^[12]CE_L&

CE_R≥ V_IH, f = f_MAX

Com’l.

25 95

25 85

85 120

70 mA

Indust.

Standby Current (One Port Com’l.

115 175

10 250

105 135

105 165

165 210

95 155

105 165

85 140 mA

TTL Level)^[12]CE_L| CE_R

V_IH, f = f_MAX

≥

Indust.

Standby Current (Both

Com’l.

10 250

10 250 µA

µA

Ports CMOS Level)^[12]CE_L

Indust.

& CE_R≥ V_CC– 0.2V, f = 0

Standby Current (One Port Com’l.

95 125

125 170

85 115

95 125

75 100 mA

CMOS Level)^[12]CE_L| CE_R

Indust.

≥ V_IH, f = f_MAX

Capacitance

Parameter

Description

Input Capacitance

Output Capacitance

Test Conditions

Max.

Unit

C_IN

T_A= 25°C, f = 1 MHz,

V_CC= 3.3V

C_OUT

Note:

12. CE_Land CE_Rare internal signals. To select either the left or right port, both CE₀and CE₁must be asserted to their active states (CE₀≤ V_ILand CE₁≥ V_IH).

Document #: 38-06056 Rev. **

Page 5 of 19

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与CY7C09369V相关器件

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CY7C09369V-10AC	CYPRESS	获取价格	Multi-Port SRAM, 32KX9, 10ns, CMOS, PQFP100, PLASTIC, TQFP-100
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CY7C09369V-12AI	CYPRESS	获取价格	Dual-Port SRAM, 16KX18, 12ns, CMOS, PQFP100, PLASTIC, TQFP-100
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CY7C09369V-6ACT	CYPRESS	获取价格	暂无描述
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