Datasheet > CY7C09369V

CY7C09369V

更新时间： 2022-04-23 23:00:11

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		/
页数	文件大小	规格书
19页	348K
描述
3.3V 16K/32K/64K x 16/18 Synchronous Dual-Port Static RAM

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CY7C09369V 数据手册

CY7C09269V/79V/89V

CY7C09369V/79V/89V

A HIGH on CE₀or LOW on CE₁for one clock cycle will power

down the internal circuitry to reduce the static power consump-

tion. The use of multiple Chip Enables allows easier banking

of multiple chips for depth expansion configurations. In the

pipelined mode, one cycle is required with CE₀LOW and CE₁

HIGH to reactivate the outputs.

Functional Description

The CY7C09269V/79V/89V and CY7C09369V/79V/89V are

high-speed 3.3V synchronous CMOS 16K, 32K, and 64K x

16/18 dual-port static RAMs. Two ports are provided, permit-

ting independent, simultaneous access for reads and writes to

any location in memory.^[6]Registers on control, address, and

data lines allow for minimal set-up and hold times. In pipelined

output mode, data is registered for decreased cycle time.

Clock to data valid t_CD2= 6.5 ns^{[1, 2]}(pipelined). Flow-through

mode can also be used to bypass the pipelined output register

to eliminate access latency. In flow-through mode data will be

available t_CD1= 18 ns after the address is clocked into the

device. Pipelined output or flow-through mode is selected via

the FT/Pipe pin.

Counter enable inputs are provided to stall the operation of the

address input and utilize the internal address generated by the

internal counter for fast interleaved memory applications. A

port’s burst counter is loaded with the port’s Address Strobe

(ADS). When the port’s Count Enable (CNTEN) is asserted,

the address counter will increment on each LOW to HIGH tran-

sition of that port’s clock signal. This will read/write one word

from/into each successive address location until CNTEN is

deasserted. The counter can address the entire memory array

and will loop back to the start. Counter Reset (CNTRST) is

used to reset the burst counter.

Each port contains a burst counter on the input address regis-

ter. The internal write pulse width is independent of the LOW

to HIGH transition of the clock signal. The internal write pulse

is self-timed to allow the shortest possible cycle times.

All parts are available in 100-pin Thin Quad Plastic Flatpack

(TQFP) packages.

Pin Configurations

100-Pin TQFP (Top View)

100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76

A9L

A10L

A11L

A12L

A13L

A14L

A15L

A9R

A10R

A11R

A12R

A13R

A14R

A15R

[7]

[8]

[7]

[8]

LBL

LBR

UBL

UBR

CE0R

CE1R

CY7C09289V (64K x 16)

CY7C09279V (32K x 16)

CY7C09269V (16K x 16)

CE0L

CE1L

CNTRSTL

VCC

CNTRSTR

GND

R/WL

R/WR

OEL

OER

[9]

FT/PIPEL

GND

FT/PIPER

GND

I/O15L

I/O14L

I/O13L

I/O12L

I/O15R

I/O14R

I/O13R

I/O12R

I/O11R

I/O10R

I/O11L

I/O10L

26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

Notes:

6. When writing simultaneously to the same location, the final value cannot be guaranteed.

7. This pin is NC for CY7C09269V.

8. This pin is NC for CY7C09269V and CY7C09279V.

9. For CY7C09269V and CY7C09279V, pin #18 connected to V_CCis pin compatible to an IDT 5V x16 pipelined device; connecting pin #18 and #58 to GND is pin

compatible to an IDT 5V x16 flow-through device.

Document #: 38-06056 Rev. **

Page 2 of 19

123 4 5 6 7...19

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与CY7C09369V相关器件

型号	品牌	获取价格	描述	数据表
CY7C09369V-10AC	CYPRESS	获取价格	Multi-Port SRAM, 32KX9, 10ns, CMOS, PQFP100, PLASTIC, TQFP-100
CY7C09369V-12AC	CYPRESS	获取价格	3.3V 16K/32K/64K x 16/18 Synchronous Dual-Port Static RAM
CY7C09369V-12AI	CYPRESS	获取价格	Dual-Port SRAM, 16KX18, 12ns, CMOS, PQFP100, PLASTIC, TQFP-100
CY7C09369V-12AXC	CYPRESS	获取价格	3.3V 16K/32K/64K x 16/18 Synchronous Dual-Port Static RAM
CY7C09369V-6AC	CYPRESS	获取价格	3.3V 16K/32K/64K x 16/18 Synchronous Dual-Port Static RAM
CY7C09369V-6ACT	CYPRESS	获取价格	暂无描述
CY7C09369V-6AXC	CYPRESS	获取价格	3.3V 16K/32K/64K x 16/18 Synchronous Dual-Port Static RAM
CY7C09369V-6AXC	ROCHESTER	获取价格	16KX18 DUAL-PORT SRAM, 6.5ns, PQFP100, LEAD FREE, PLASTIC, MS-026, TQFP-100
CY7C09369V-7AC	CYPRESS	获取价格	3.3V 16K/32K/64K x 16/18 Synchronous Dual-Port Static RAM
CY7C09369V-7AI	CYPRESS	获取价格	3.3V 16K/32K/64K x 16/18 Synchronous Dual-Port Static RAM

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