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CY7C09369-12AC PDF预览

CY7C09369-12AC

更新时间: 2024-11-07 15:44:55
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 时钟静态存储器内存集成电路
页数 文件大小 规格书
17页 540K
描述
Dual-Port SRAM, 16KX18, 12ns, CMOS, PQFP100, PLASTIC, TQFP-100

CY7C09369-12AC 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:QFP包装说明:PLASTIC, TQFP-100
针数:100Reach Compliance Code:not_compliant
ECCN代码:3A991.B.2.BHTS代码:8542.32.00.41
风险等级:5.83最长访问时间:12 ns
其他特性:AUTOMATIC POWER DOWN最大时钟频率 (fCLK):50 MHz
I/O 类型:COMMONJESD-30 代码:S-PQFP-G100
JESD-609代码:e0长度:14 mm
内存密度:294912 bit内存集成电路类型:DUAL-PORT SRAM
内存宽度:18功能数量:1
端口数量:2端子数量:100
字数:16384 words字数代码:16000
工作模式:SYNCHRONOUS最高工作温度:70 °C
最低工作温度:组织:16KX18
输出特性:3-STATE封装主体材料:PLASTIC/EPOXY
封装代码:LFQFP封装等效代码:QFP100,.63SQ,20
封装形状:SQUARE封装形式:FLATPACK, LOW PROFILE, FINE PITCH
并行/串行:PARALLEL峰值回流温度(摄氏度):NOT SPECIFIED
电源:5 V认证状态:Not Qualified
座面最大高度:1.6 mm最大待机电流:0.0005 A
最小待机电流:4.5 V子类别:SRAMs
最大压摆率:0.3 mA最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子面层:Tin/Lead (Sn/Pb)
端子形式:GULL WING端子节距:0.5 mm
端子位置:QUAD处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:14 mmBase Number Matches:1

CY7C09369-12AC 数据手册

 浏览型号CY7C09369-12AC的Datasheet PDF文件第2页浏览型号CY7C09369-12AC的Datasheet PDF文件第3页浏览型号CY7C09369-12AC的Datasheet PDF文件第4页浏览型号CY7C09369-12AC的Datasheet PDF文件第5页浏览型号CY7C09369-12AC的Datasheet PDF文件第6页浏览型号CY7C09369-12AC的Datasheet PDF文件第7页 
025/0251  
CY7C09269/79/89  
CY7C09369/79/89  
PRELIMINARY  
16K/32K/64K x16/18  
Synchronous Dual Port Static RAM  
• Low operating power  
Features  
Active= 195 mA (typical)  
• True Dual-Ported memory cells which allow simulta-  
neous access of the same memory location  
Standby= 0.05 mA (typical)  
• Fully synchronous interface for easier operation  
• Burst counters increment addresses internally  
— Shorten cycle times  
• 6 Flow-Through/Pipelined devices  
— 16K x 16/18 organization (CY7C09269/369)  
— 32K x 16/18 organization (CY7C09279/379)  
— 64K x 16/18 organization (CY7C09289/389)  
• 3 Modes  
Minimize bus noise  
Supported in Flow-Through and Pipelined modes  
• Dual Chip Enables for easy depth expansion  
• Upper and Lower Byte Controls for Bus Matching  
• Automatic power-down  
• Commercial and Industrial temperature ranges  
• Available in 100-pin TQFP  
— Flow-Through  
— Pipelined  
— Burst  
• Pipelined output mode on both ports allows fast  
100-MHz cycle time  
• 0.35-micron CMOS for optimum speed/power  
• Pin-compatible and functionally equivalent to  
IDT709269, IDT70927, and IDT709279  
• High-speed clock to data access 6.5/7.5/9/12 ns (max.)  
Logic Block Diagram  
R/WL  
UBL  
R/WR  
UBR  
CE0L  
CE1L  
LBL  
CE0R  
CE1R  
LBR  
1
1
0
0
0/1  
0/1  
OEL  
OER  
1b 0b 1a 0a  
0a 1a 0b 1b  
a b 0/1  
0/1  
b
a
FT/PipeL  
FT/PipeR  
8/9  
8/9  
8/9  
8/9  
[1]  
[1]  
I/O8/9L–I/O15/17L  
I/O8/9R–I/O15/17R  
I/O  
Control  
I/O  
Control  
[2]  
[2]  
I/O0L–I/O7/8L  
I/O0R–I/O  
7/8R  
14/15/16  
14/15/16  
[3]  
[3]  
A
0L–A  
A
–A  
13/14/15L  
0R  
13/14/15R  
CLKR  
Counter/  
Address  
Register  
Decode  
Counter/  
Address  
Register  
Decode  
CLKL  
ADSL  
True Dual-Ported  
RAM Array  
ADSR  
CNTENL  
CNTENR  
CNTRSTL  
CNTRSTR  
Notes:  
1. I/O8–I/O15 for x16 devices; I/O9–I/O17 for x18 devices.  
2. I/O0–I/O7 for x16 devices. I/O0–I/O8 for x18 devices.  
3. A0–A13 for 16K; A0–A14 for 32K; A0–A15 for 64K devices.  
For the most recent information, visit the Cypress web site at www.cypress.com  
Cypress Semiconductor Corporation 3901 North First Street San Jose CA 95134  
408-943-2600  
November 23, 1998  

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