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CY62162G30-45BGXI PDF预览

CY62162G30-45BGXI

更新时间: 2024-02-02 07:33:35
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 静态存储器内存集成电路
页数 文件大小 规格书
20页 382K
描述
Standard SRAM, 512KX32, 45ns, CMOS, PBGA119, 14 X 22 MM, 2.40 MM HEIGHT, LEAD FREE, PLASTIC, BGA-119

CY62162G30-45BGXI 技术参数

是否Rohs认证: 符合生命周期:Active
包装说明:HBGA,Reach Compliance Code:compliant
ECCN代码:3A991.B.2.BHTS代码:8542.32.00.41
风险等级:5.8最长访问时间:45 ns
JESD-30 代码:R-PBGA-B119长度:22 mm
内存密度:16777216 bit内存集成电路类型:STANDARD SRAM
内存宽度:32功能数量:1
端子数量:119字数:524288 words
字数代码:512000工作模式:ASYNCHRONOUS
最高工作温度:85 °C最低工作温度:-40 °C
组织:512KX32封装主体材料:PLASTIC/EPOXY
封装代码:HBGA封装形状:RECTANGULAR
封装形式:GRID ARRAY, HEAT SINK/SLUG并行/串行:PARALLEL
峰值回流温度(摄氏度):NOT SPECIFIED座面最大高度:2.4 mm
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):2.2 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子形式:BALL端子节距:1.27 mm
端子位置:BOTTOM处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:14 mmBase Number Matches:1

CY62162G30-45BGXI 数据手册

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CY62162G/CY62162GE MoBL®  
16-Mbit (512 K × 32) Static RAM  
with Error-Correcting Code (ECC)  
16-Mbit (512  
K × 32) Static RAM with Error-Correcting Code (ECC)  
feature that reduces power consumption when addresses are  
not toggling. Placing the device into standby mode reduces  
power consumption by more than 99% when deselected (CE1  
HIGH or CE2 LOW or BA-D HIGH). The input and output pins  
(I/O0 through I/O31) are placed in a high impedance state when  
deselected (CE1 HIGH or CE2 LOW) or outputs are disabled (OE  
HIGH) or the byte selects are disabled (BA-D HIGH).  
Features  
Ultra-low standby power  
Typical standby current: 5.5 A  
Maximum standby current: 16 A  
High speed: 45 ns / 55 ns  
To write to the device, take chip enables (CE1 LOW, CE2 HIGH)  
and write enable (WE) input LOW. If byte enable A (BA) is LOW,  
then data from I/O pins (I/O0 through I/O7) is written into the  
location specified on the address pins (A0 through A18). If byte  
enable B (BB) is LOW, then data from I/O pins (I/O8 through  
I/O15) is written into the location specified on the address pins  
(A0 through A18). Likewise, BC and BD correspond with the I/O  
pins I/O16 to I/O23 and I/O24 to I/O31, respectively.  
Embedded error-correcting code (ECC) for single-bit error  
correction  
Wide voltage range: 1.65 V to 2.2 V, 2.2 V to 3.6 V  
1.0-V data retention  
Transistor-transistor logic (TTL) compatible inputs and outputs  
ERR pin to indicate 1-bit error detection and correction  
Easy memory expansion with CE1 and CE2 features  
To read from the device, take chip enables (CE1 LOW, CE2  
HIGH), and output enable (OE) LOW while forcing the write  
enable (WE) HIGH. If the first byte enable (BA) is LOW, then data  
from the memory location specified by the address pins appear  
on I/O0 to I/O7. If byte enable (BB) is LOW, then data from  
memory appears on I/O8 to I/O15. Likewise, BC and BD  
correspond to the third and fourth bytes. During Read operation,  
in case of a single bit error detection and correction, ERR is  
asserted HIGH[1]. See the Truth Table – CY62162G /  
CY62162GE on page 15 for a complete description of read and  
write modes.  
Available in Pb-free 119-ball PBGA package, 512 K × 32 bits  
SRAM  
Functional Description  
The CY62162G and CY62162GE devices are high performance  
CMOS MoBL SRAM organized as 512K words by 32-bits. Both  
CY62162G and CY62162GE are available with dual chip  
enables. CY62162GE includes an error indication pin that  
signals the host processor in the case of a single bit  
error-detection and correction event. It is ideal for providing More  
Battery Life™ (MoBL®) in portable applications such as cellular  
telephones. The device also has an automatic power down  
CY62162G and CY62162GE devices are available in a 119-ball  
PBGA package with center power and ground pinout.  
Note  
1. This device does not support automatic write-back on error detection.  
Cypress Semiconductor Corporation  
Document Number: 001-81598 Rev. *D  
198 Champion Court  
San Jose, CA 95134-1709  
408-943-2600  
Revised January 3, 2018  
 

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