CY62167DV18L-55BVI

更新时间： 2024-01-31 14:10:03

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		/
页数	文件大小	规格书
11页	163K
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CY62167DV18L-55BVI 数据手册

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CY62167DV18

MoBL2™

PRELIMINARY

16M (1024K x 16) Static RAM

toggling. The device can be put into standby mode reducing

power consumption by more than 99% when deselected Chip

Enable 1 (CE₁) HIGH or Chip Enable 2 (CE₂) LOW or both

BHE and BLE are HIGH. The input/output pins (I/O₀through

I/O₁₅) are placed in a high-impedance state when: deselected

Chip Enable 1 (CE₁) HIGH or Chip Enable 2 (CE₂) LOW,

outputs are disabled (OE HIGH), both Byte High Enable and

Byte Low Enable are disabled (BHE, BLE HIGH) or during a

write operation (Chip Enable 1 (CE₁) LOW and Chip Enable 2

(CE₂) HIGH and WE LOW).

Features

• Very high speed: 55 ns and 70 ns

• Voltage range: 1.65V to 1.95V

• Ultra-low active power

— Typical active current: 1.5 mA @ f = 1 MHz

— Typical active current: 15 mA @ f = f_MAX

• Ultra-low standby power

• Easy memory expansion with CE</>_{1</>, CE2</> and OE</>}

features

Writing to the device is accomplished by taking Chip Enable 1

(CE₁) LOW and Chip Enable 2 (CE₂) HIGH and Write Enable

(WE) input LOW. If Byte Low Enable (BLE) is LOW, then das

pins (A₀through A₁₉). If Byte High Enable (BHE) is LOW, then

data from I/O pins (I/O₈through I/O₁₅) is written into the

location specified on the ad

• Automatic power-down when deselected

• CMOS for optimum speed/power

• Packages offered in a 48-ball FBGA

Functional Description^[1]

Reading from the device is accomplished by taking Chip

Enable 1 (CE₁) LOW and Chip Enable 2 (CE₂) HIGH and

Output Enable (OE) LOW while forcing the Write Enable (WE)

HIGH. If Byte Low Enable (<>O₇. If Byte High Enable (BHE)

The CY62167DV18 is a high-performance CMOS static RAM

organized as 1024K words by 16 bits. This device features

advanced circuit design to provide ultra-low active current.

This is ideal for providing More Battery Life (MoBL^®) in

portable applications such as cellular telephones. The device

also has an automatic power-down feature that significantly

reduces power consumption by 99% when addresses are not

is LOW, then data from memory will appear on I/O₈to I/O₁₅

See the truth table at the back of this data sheet for a complete

description of read and write modes.

Logic Block Diagram

DATA IN DRIVERS

A₁₀

A ₉

A ₈

A ₇

A ₆

A ₅

A ₄

A ₃

1024K x 16

RAM ARRAY

2048 x 512 x 16

I/O₀–I/O₇

I/O₈–I/O₁₅

A ₂

A ₁

A ₀

COLUMN DECODER

BHE

CE₂

CE₁

BLE

Po we r-d o wn

Circ uit

CE₂

CE₁

BHE

BLE

Note:

1. For best practice recommendations, please refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com.

Cypress Semiconductor Corporation

Document #: 38-05326 Rev. *A

•

3901 North First Street

•

San Jose, CA 95134

•

408-943-2600

Revised February 10, 2003

12 3 4 5 6 7...11

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与CY62167DV18L-55BVI相关器件

型号	品牌	获取价格	描述	数据表
CY62167DV18L-70	CYPRESS	获取价格	16M (1024K x 16) Static RAM
CY62167DV18L-70BVI	CYPRESS	获取价格	Standard SRAM, 1MX16, 70ns, CMOS, PBGA48, 8 X 9.50 MM, 1 MM HEIGHT, BGA-48
CY62167DV18LL-55	CYPRESS	获取价格	16M (1024K x 16) Static RAM
CY62167DV18LL-55BVXI	CYPRESS	获取价格	16-Mbit (1M x 16) Static RAM
CY62167DV18LL-55BVXIT	CYPRESS	获取价格	Standard SRAM, 1MX16, 55ns, CMOS, PBGA48, 8 X 9.50 MM, 1 MM HEIGHT, LEAD FREE, BGA-48
CY62167DV18LL-70	CYPRESS	获取价格	16M (1024K x 16) Static RAM
CY62167DV20	CYPRESS	获取价格	16-Mb (1024K x 16) Static RAM
CY62167DV20L	CYPRESS	获取价格	16-Mb (1024K x 16) Static RAM
CY62167DV20L-55BVI	CYPRESS	获取价格	16-Mb (1024K x 16) Static RAM
CY62167DV20L-70BVI	CYPRESS	获取价格	16-Mb (1024K x 16) Static RAM

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