Datasheet > CY62162GE18

CY62162GE18

更新时间： 2024-02-23 18:51:12

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		/
页数	文件大小	规格书
20页	321K
描述
16-Mbit (512 K Ã 32) Static RAM with Error-Correcting Code (ECC)

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CY62162GE18 数据手册

CY62162G/CY62162GE MoBL^®

16-Mbit (512 K × 32) Static RAM

with Error-Correcting Code (ECC)

16-Mbit (512

K × 32) Static RAM with Error-Correcting Code (ECC)

feature that reduces power consumption when addresses are

not toggling. Placing the device into standby mode reduces

power consumption by more than 99% when deselected (CE₁

HIGH or CE₂LOW or B_A-DHIGH). The input and output pins

(I/O₀through I/O₃₁) are placed in a high impedance state when

deselected (CE₁HIGH or CE₂LOW) or outputs are disabled (OE

HIGH) or the byte selects are disabled (B_A-DHIGH).

Features

■ Ultra-low standby power

❐ Typical standby current: 5.5 μA

❐ Maximum standby current: 16 μA

■ High speed: 45 ns / 55 ns

To write to the device, take chip enables (CE₁LOW, CE₂HIGH)

and write enable (WE) input LOW. If byte enable A (B_A) is LOW,

then data from I/O pins (I/O₀through I/O₇) is written into the

location specified on the address pins (A₀through A₁₈). If byte

enable B (B_B) is LOW, then data from I/O pins (I/O₈through

I/O₁₅) is written into the location specified on the address pins

(A₀through A₁₈). Likewise, B_Cand B_Dcorrespond with the I/O

pins I/O₁₆to I/O₂₃and I/O₂₄to I/O₃₁, respectively.

■ Embedded error-correcting code (ECC) for single-bit error

correction

■ Wide voltage range: 1.65 V to 2.2 V, 2.2 V to 3.6 V

■ 1.0-V data retention

■ Transistor-transistor logic (TTL) compatible inputs and outputs

■ ERR pin to indicate 1-bit error detection and correction

■ Easy memory expansion with CE₁and CE₂features

To read from the device, take chip enables (CE₁LOW, CE₂

HIGH), and output enable (OE) LOW while forcing the write

enable (WE) HIGH. If the first byte enable (B_A) is LOW, then data

from the memory location specified by the address pins appear

on I/O₀to I/O₇. If byte enable (B_B) is LOW, then data from

memory appears on I/O₈to I/O₁₅. Likewise, B_Cand B_D

correspond to the third and fourth bytes. During Read operation,

in case of a single bit error detection and correction, ERR is

asserted HIGH^[1]. See the Truth Table – CY62162G /

CY62162GE on page 15 for a complete description of read and

write modes.

■ Available in Pb-free 119-ball PBGA package, 512 K × 32 bits

SRAM

Functional Description

The CY62162G and CY62162GE devices are high performance

CMOS MoBL SRAM organized as 512K words by 32-bits. Both

CY62162G and CY62162GE are available with dual chip

enables. CY62162GE includes an error indication pin that

signals the host processor in the case of a single bit

error-detection and correction event. It is ideal for providing More

Battery Life™ (MoBL^®) in portable applications such as cellular

telephones. The device also has an automatic power down

CY62162G and CY62162GE devices are available in a 119-ball

PBGA package with center power and ground pinout.

Note

1. This device does not support automatic write-back on error detection.

Cypress Semiconductor Corporation

Document Number: 001-81598 Rev. *C

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised July 31, 2015

12 3 4 5 6 7...20

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与CY62162GE18相关器件

型号	品牌	获取价格	描述	数据表
CY62162GE30	CYPRESS	获取价格	16-Mbit (512 K Ã 32) Static RAM with Error-C
CY62167DV18	CYPRESS	获取价格	16M (1024K x 16) Static RAM
CY62167DV18_07	CYPRESS	获取价格	16-Mbit (1M x 16) Static RAM
CY62167DV18L-55	CYPRESS	获取价格	16M (1024K x 16) Static RAM
CY62167DV18L-55BVI	CYPRESS	获取价格	暂无描述
CY62167DV18L-70	CYPRESS	获取价格	16M (1024K x 16) Static RAM
CY62167DV18L-70BVI	CYPRESS	获取价格	Standard SRAM, 1MX16, 70ns, CMOS, PBGA48, 8 X 9.50 MM, 1 MM HEIGHT, BGA-48
CY62167DV18LL-55	CYPRESS	获取价格	16M (1024K x 16) Static RAM
CY62167DV18LL-55BVXI	CYPRESS	获取价格	16-Mbit (1M x 16) Static RAM
CY62167DV18LL-55BVXIT	CYPRESS	获取价格	Standard SRAM, 1MX16, 55ns, CMOS, PBGA48, 8 X 9.50 MM, 1 MM HEIGHT, LEAD FREE, BGA-48

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