Datasheet > CY62157H

CY62157H

更新时间： 2024-11-22 01:14:27

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		/
页数	文件大小	规格书
20页	384K
描述
8-Mbit (512K words Ã 16-bit) Static RAM with Error-Correcting Code (ECC)

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CY62157H 数据手册

CY62157H MoBL^®

8-Mbit (512K words × 16-bit) Static RAM

with Error-Correcting Code (ECC)

8-Mbit (512K words

× 16-bit) Static RAM with Error-Correcting Code (ECC)

Data writes are performed by asserting the Write Enable input

(WE LOW), and providing the data and address on device data

(I/O₀through I/O₁₅) and address (A₀through A₁₈) pins

respectively. The Byte High/Low Enable (BHE, BLE) inputs

control byte writes, and write data on the corresponding I/O lines

to the memory location specified. BHE controls I/O₈through

I/O₁₅and BLE controls I/O₀through I/O₇.

Features

■ Ultra-low standby current

❐ Typical standby current: 5.5A

❐ Maximum standby current: 16 A

■ High speed: 45 ns

Data reads are performed by asserting the Output Enable (OE)

input and providing the required address on the address lines.

Read data is accessible on I/O lines (I/O₀through I/O₁₅). Byte

accesses can be performed by asserting the required byte

enable signal (BHE, BLE) to read either the upper byte or the

lower byte of data from the specified address location.

■ Voltage range: 2.2 V to 3.6 V

■ Embedded Error-Correcting Code (ECC) for single-bit error

correction

■ 1.0 V data retention

■ Transistor-transistor logic (TTL) compatible inputs and outputs

All I/Os (I/O₀through I/O₁₅) are placed in a high impedance state

when the device is deselected (CE₁HIGH / CE₂LOW for dual

chip enable device), or control signals are de-asserted (OE, BLE,

BHE).

■ Available in Pb-free 48-ball VFBGA and 48-pin TSOP I

packages

Functional Description

These devices also have a unique “Byte Power down” feature,

where, if both the Byte Enables (BHE and BLE) are disabled, the

devices seamlessly switch to standby mode irrespective of the

state of the chip enable(s), thereby saving power.

CY62157H is a high-performance CMOS low-power (MoBL)

SRAM device with Embedded Error-Correcting Code. ECC logic

can detect and correct single bit error in accessed location.

The CY62157H device is available in a Pb-free 48-ball VFBGA

and 48-pin TSOP I packages. The logic block diagram is on

page 2.

This device is offered in dual chip enable option. Dual chip

enable devices are accessed by asserting both chip enable

inputs – CE₁as LOW and CE₂as HIGH.

Product Portfolio

Power Dissipation

Operating I_CC, (mA)

Features and

Options

(see the Pin

Configurations

section)

Standby, I_SB2(µA)

Product

Range

V_CCRange (V) Speed (ns)

f = f_max

Typ ^[1]

Max

Typ ^[1]

Max

CY62157H30

Dual Chip

Enable

Industrial

2.2 V–3.6 V

5.5

Note

1. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at V = 3 V (for V range of 2.2 V–3.6 V), T = 25 °C.

Cypress Semiconductor Corporation

Document Number: 001-88316 Rev. *E

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised February 8, 2018

12 3 4 5 6 7...20

中文翻译

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