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CY62158CV25LL-70BAI PDF预览

CY62158CV25LL-70BAI

更新时间: 2024-09-14 22:18:27
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 存储内存集成电路静态存储器
页数 文件大小 规格书
12页 259K
描述
1024K x 8 MoBL Static RAM

CY62158CV25LL-70BAI 技术参数

是否Rohs认证:不符合生命周期:Obsolete
零件包装代码:BGA包装说明:6 X 10 MM, 1.20 MM HEIGHT, FBGA-48
针数:48Reach Compliance Code:not_compliant
ECCN代码:3A991.B.2.AHTS代码:8542.32.00.41
风险等级:5.83Is Samacsys:N
最长访问时间:70 nsI/O 类型:COMMON
JESD-30 代码:R-PBGA-B48JESD-609代码:e0
长度:10 mm内存密度:8388608 bit
内存集成电路类型:STANDARD SRAM内存宽度:8
功能数量:1端子数量:48
字数:1048576 words字数代码:1000000
工作模式:ASYNCHRONOUS最高工作温度:85 °C
最低工作温度:-40 °C组织:1MX8
输出特性:3-STATE封装主体材料:PLASTIC/EPOXY
封装代码:TFBGA封装等效代码:BGA48,6X8,30
封装形状:RECTANGULAR封装形式:GRID ARRAY, THIN PROFILE, FINE PITCH
并行/串行:PARALLEL电源:2.5 V
认证状态:Not Qualified座面最大高度:1.2 mm
最大待机电流:0.00001 A最小待机电流:1.5 V
子类别:SRAMs最大压摆率:0.015 mA
最大供电电压 (Vsup):2.7 V最小供电电压 (Vsup):2.2 V
标称供电电压 (Vsup):2.5 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:Tin/Lead (Sn/Pb)端子形式:BALL
端子节距:0.75 mm端子位置:BOTTOM
宽度:6 mmBase Number Matches:1

CY62158CV25LL-70BAI 数据手册

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CY62158CV25/30/33  
MoBL™  
1024K x 8 MoBL Static RAM  
in portable applications such as cellular telephones. The de-  
vice also has an automatic power-down feature that signifi-  
cantly reduces power consumption by 80% when addresses  
are not toggling. The device can be put into standby mode  
reducing power consumption by more than 99% when dese-  
lected (CE1 HIGH or CE2 LOW).  
Features  
High Speed  
55 ns and 70 ns availability  
Voltage range:  
CY62158CV25: 2.2V2.7V  
CY62158CV30: 2.7V3.3V  
CY62158CV33: 3.0V3.6V  
Ultra low active power  
Typical active current: 1.5 mA @ f = 1 MHz  
Writing to the device is accomplished by taking Chip Enable 1  
(CE1) and Write Enable (WE) inputs LOW and Chip Enable 2  
(CE2) HIGH. Data on the eight I/O pins (I/O0 through I/O7) is  
then written into the location specified on the address pins (A0  
through A19).  
Reading from the device is accomplished by taking Chip En-  
able 1 (CE1) and Output Enable (OE) LOW and Chip Enable  
2 (CE2) HIGH while forcing Write Enable (WE) HIGH. Under  
these conditions, the contents of the memory location speci-  
fied by the address pins will appear on the I/O pins.  
Typicalactivecurrent: 5.5mA @ f =fmax(70nsspeed)  
Low standby power  
Easy memory expansion with CE1, CE2 and OE features  
Automatic power-down when deselected  
CMOS for optimum speed/power  
The eight input/output pins (I/O0 through I/O7) are placed in a  
high-impedance state when the device is deselected (CE1  
LOW and CE2 HIGH), the outputs are disabled (OE HIGH), or  
during a write operation (CE1 LOW and CE2 HIGH and WE  
LOW).  
Functional Description  
The CY62158CV25/30/33 are high-performance CMOS static  
RAMs organized as 1024K words by 8 bits. This device fea-  
tures advanced circuit design to provide ultra-low active cur-  
rent. This is ideal for providing More Battery Life(MoBL)  
The CY62158CV25/30/33 are available in a 48-ball FBGA  
package.  
Logic Block Diagram  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
0
Data in Drivers  
A
0
1
2
3
4
5
6
7
8
1
2
3
4
5
A
A
A
A
A
A
1024K x 8  
ARRAY  
A
A
A
9
10  
11  
A
A
A
12  
6
7
POWER  
DOWN  
COLUMN  
DECODER  
CE1  
CE2  
I/O  
WE  
OE  
Cypress Semiconductor Corporation  
3901 North First Street  
San Jose  
CA 95134  
408-943-2600  
Document #: 38-05019 Rev. *C  
Revised April 24, 2002  

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