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CY62158DV30L-70BVI PDF预览

CY62158DV30L-70BVI

更新时间: 2024-11-18 04:53:27
品牌 Logo 应用领域
赛普拉斯 - CYPRESS /
页数 文件大小 规格书
11页 410K
描述
8-Mbit (1024K x 8) MoBL Static RAM

CY62158DV30L-70BVI 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:BGA包装说明:6 X 8 MM, 1 MM HEIGHT, VFBGA-48
针数:48Reach Compliance Code:not_compliant
ECCN代码:3A991.B.2.AHTS代码:8542.32.00.41
风险等级:5.87最长访问时间:70 ns
I/O 类型:COMMONJESD-30 代码:R-PBGA-B48
JESD-609代码:e0长度:8 mm
内存密度:8388608 bit内存集成电路类型:STANDARD SRAM
内存宽度:8湿度敏感等级:3
功能数量:1端子数量:48
字数:1048576 words字数代码:1000000
工作模式:ASYNCHRONOUS最高工作温度:85 °C
最低工作温度:-40 °C组织:1MX8
输出特性:3-STATE封装主体材料:PLASTIC/EPOXY
封装代码:VFBGA封装等效代码:BGA48,6X8,30
封装形状:RECTANGULAR封装形式:GRID ARRAY, VERY THIN PROFILE, FINE PITCH
并行/串行:PARALLEL峰值回流温度(摄氏度):240
电源:2.5/3.3 V认证状态:Not Qualified
座面最大高度:1 mm最大待机电流:0.00001 A
最小待机电流:1.5 V子类别:SRAMs
最大压摆率:0.02 mA最大供电电压 (Vsup):3.6 V
最小供电电压 (Vsup):2.2 V标称供电电压 (Vsup):3 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:TIN LEAD
端子形式:BALL端子节距:0.75 mm
端子位置:BOTTOM处于峰值回流温度下的最长时间:30
宽度:6 mm

CY62158DV30L-70BVI 数据手册

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CY62158DV30  
MoBL  
8-Mbit (1024K x 8) MoBLStatic RAM  
This is ideal for providing More Battery Life™ (MoBL) in  
portable applications such as cellular telephones. The device  
also has an automatic power-down feature that significantly  
reduces power consumption. The device can be put into  
standby mode reducing power consumption by 85% when  
deselected (CE1 HIGH or CE2 LOW).  
Features  
• Very high speed: 45 ns, 55 ns and 70 ns  
— Wide voltage range: 2.20V – 3.60V  
• Ultra-low active power  
— Typical active current:1.5 mA @ f = 1 MHz  
— Typical active current: 12 mA @ f = fmax  
• Ultra-low standby power  
Writing to the device is accomplished by taking Chip Enable 1  
(CE1) and Write Enable (WE) inputs LOW and Chip Enable 2  
(CE2) HIGH. Data on the eight I/O pins (I/O0 through I/O7) is  
then written into the location specified on the address pins (A0  
• Easy memory expansion with CE1, CE2, and OE  
through A19).  
features  
Reading from the device is accomplished by taking Chip  
Enable 1 (CE1) and Output Enable (OE) LOW and Chip  
Enable 2 (CE2) HIGH while forcing Write Enable (WE) HIGH.  
Under these conditions, the contents of the memory location  
specified by the address pins will appear on the I/O pins.  
The eight input/output pins (I/O0 through I/O7) are placed in a  
high-impedance state when the device is deselected (CE1  
LOW and CE2 HIGH), the outputs are disabled (OE HIGH), or  
during a write operation (CE1 LOW and CE2 HIGH and WE  
LOW). See the truth table for a complete description of read  
and write modes.  
• Automatic power-down when deselected  
• CMOS for optimum speed/power  
• Packages offered in a 48-ball BGA, 48-pin TSOPI, and  
44-pin TSOPII  
Functional Description[1]  
The CY62158DV30 is a high-performance CMOS static RAMs  
organized as 1024K words by 8 bits. This device features  
advanced circuit design to provide ultra-low active current.  
Logic Block Diagram  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
0
Data in Drivers  
A0  
A1  
A2  
A3  
A4  
1
2
A
A5  
A6  
3
4
5
1024K x 8  
A7  
ARRAY  
A98  
A10  
A11  
A12  
6
7
POWER  
DOWN  
COLUMN  
CE  
CE  
1
2
DECODER  
I/O  
WE  
OE  
Note:  
1. For best practice recommendations, please refer to the Cypress application note entitled System Design Guidelines, available at http://www.cypress.com.  
Cypress Semiconductor Corporation  
3901 North First Street  
San Jose, CA 95134  
408-943-2600  
Document #: 38-05391 Rev. *D  
Revised June 17, 2004  
[+] Feedback  

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